From 3d193b0275850c23d73b5e7502b8f879fe51c836 Mon Sep 17 00:00:00 2001 From: Kyle Isom Date: Wed, 2 Jan 2019 16:29:31 -0800 Subject: [PATCH] fpga: add icestick segment LCD demo. --- fpga/icestick/SegmentLCD/SegmentLCD.v | 41 +++++++++++++++ fpga/icestick/SegmentLCD/apio.ini | 3 ++ fpga/icestick/SegmentLCD/pins.pcf | 73 +++++++++++++++++++++++++++ fpga/icestick/SegmentLCD/top.v | 32 ++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 fpga/icestick/SegmentLCD/SegmentLCD.v create mode 100644 fpga/icestick/SegmentLCD/apio.ini create mode 100644 fpga/icestick/SegmentLCD/pins.pcf create mode 100644 fpga/icestick/SegmentLCD/top.v diff --git a/fpga/icestick/SegmentLCD/SegmentLCD.v b/fpga/icestick/SegmentLCD/SegmentLCD.v new file mode 100644 index 0000000..5ea545f --- /dev/null +++ b/fpga/icestick/SegmentLCD/SegmentLCD.v @@ -0,0 +1,41 @@ +/// SegmentLCD represents a 7-segment display that takes as input a 4-bit +/// number and outputs the correct pin configuration. The pins need to be +/// wired as {G, F, E, D, C, B, A} for this to work. +/// +/// For example, +/// +/// wire [7:0] sum = 8'b00000000; +/// segment7 low ( +/// .number(sum[3:0]), +/// .out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9}) +/// ); +module SegmentLCD ( + input [3:0] number, + output reg [6:0] out +); + + always @(*) + begin + case (number) + 4'b0000: out = ~7'b0111111; // 0 + 4'b0001: out = ~7'b0000110; // 1 + 4'b0010: out = ~7'b1011011; // 2 + 4'b0011: out = ~7'b1001111; // 3 + 4'b0100: out = ~7'b1100110; // 4 + 4'b0101: out = ~7'b1101101; // 5 + 4'b0110: out = ~7'b1111101; // 6 + 4'b0111: out = ~7'b0000111; // 7 + 4'b1000: out = ~7'b1111111; // 8 + 4'b1001: out = ~7'b1100111; // 9 + 4'b1010: out = ~7'b1110111; // A + 4'b1011: out = ~7'b1111100; // B + 4'b1100: out = ~7'b0111001; // C + 4'b1101: out = ~7'b1011110; // D + 4'b1110: out = ~7'b1111001; // E + 4'b1111: out = ~7'b1110001; // F + endcase + end + +endmodule + + diff --git a/fpga/icestick/SegmentLCD/apio.ini b/fpga/icestick/SegmentLCD/apio.ini new file mode 100644 index 0000000..dfe2215 --- /dev/null +++ b/fpga/icestick/SegmentLCD/apio.ini @@ -0,0 +1,3 @@ +[env] +board = icestick + diff --git a/fpga/icestick/SegmentLCD/pins.pcf b/fpga/icestick/SegmentLCD/pins.pcf new file mode 100644 index 0000000..1f04bb0 --- /dev/null +++ b/fpga/icestick/SegmentLCD/pins.pcf @@ -0,0 +1,73 @@ +# ----------------------------------------------------------------------------- +#- Icestick constraint file (.pcf) +#- By Juan Gonzalez (Obijuan) +#- April - 2016 +#- GPL license +# ----------------------------------------------------------------------------- +# -- Pinout: http://www.pighixxx.com/test/2016/02/icestick-pinout/ +# -- Guide: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/icestickusermanual.pdf + +# -- Icestick leds map +# +# D1 +# D4 D5 D2 +# D3 +# +# -- D1-D4: Red leds +# -- D5: green led + + +# ------------ Red leds ------------------------------------------------------ +set_io --warn-no-port D1 99 +set_io --warn-no-port D2 98 +set_io --warn-no-port D3 97 +set_io --warn-no-port D4 96 + +# ------------ Green led ----------------------------------------------------- +set_io --warn-no-port D5 95 + +# ------------------------ EXPANSION I/O ------------------------------------ +# +# -- Numeration +# +# Top Row (TR): +# v +# -------------------------------- +# | 10 9 8 7 6 5 4 3 2 1 | +# -------------------------------- +# +# Bottom Row (BR): +# +# v +# -------------------------------- +# | 10 9 8 7 6 5 4 3 2 1 | +# -------------------------------- +# +# --- FPGA pins +# +# Top Row (TR) +# v +# -------------------------------------------------- +# | 119 118 117 116 115 114 113 112 GND 3v3 | +# -------------------------------------------------- +# +# +# Bottom Row (BR) +# +# v +# ------------------------------------------------- +# | 44 45 47 48 56 60 61 62 GND 3v3 | +# ------------------------------------------------- +# +# -- Bottom Row +# set_io --warn-no-port BR3 62 +set_io --warn-no-port BR4 61 +set_io --warn-no-port BR5 60 +set_io --warn-no-port BR6 56 +set_io --warn-no-port BR7 48 +set_io --warn-no-port BR8 47 +set_io --warn-no-port BR9 45 +set_io --warn-no-port BR10 44 + +# -------------------------- SYSTEM CLOCK ------------------------------------ +set_io --warn-no-port CLK 21 diff --git a/fpga/icestick/SegmentLCD/top.v b/fpga/icestick/SegmentLCD/top.v new file mode 100644 index 0000000..d9e99cd --- /dev/null +++ b/fpga/icestick/SegmentLCD/top.v @@ -0,0 +1,32 @@ +module SegmentLCDTest ( + input CLK, + output D1, + output D2, + output D3, + output D4, + output D5, + output BR4, + output BR5, + output BR6, + output BR7, + output BR8, + output BR9, + output BR10 +); + + reg [21:0] clock_counter = 22'b00000000000000000000000; + reg [3:0] number = 4'b0000; + + SegmentLCD display ( + .number(number), + .out({BR10, BR9, BR8, BR7, BR6, BR5, BR4}) + ); + + always @(posedge CLK) begin + clock_counter <= clock_counter + 1; + if (clock_counter == 22'b1001001001111100000000) begin + number <= number + 1; + clock_counter <= 0; + end + end +endmodule