# ----------------------------------------------------------------------------- #- Icestick constraint file (.pcf) #- By Juan Gonzalez (Obijuan) #- April - 2016 #- GPL license # ----------------------------------------------------------------------------- # -- Pinout: http://www.pighixxx.com/test/2016/02/icestick-pinout/ # -- Guide: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/icestickusermanual.pdf # -- Icestick leds map # # D1 # D4 D5 D2 # D3 # # -- D1-D4: Red leds # -- D5: green led # ------------ Red leds ------------------------------------------------------ set_io --warn-no-port D1 99 set_io --warn-no-port D2 98 set_io --warn-no-port D3 97 set_io --warn-no-port D4 96 # ------------ Green led ----------------------------------------------------- set_io --warn-no-port D5 95 # ------------------------ EXPANSION I/O ------------------------------------ # # -- Numeration # # Top Row (TR): # v # -------------------------------- # | 10 9 8 7 6 5 4 3 2 1 | # -------------------------------- # # Bottom Row (BR): # # v # -------------------------------- # | 10 9 8 7 6 5 4 3 2 1 | # -------------------------------- # # --- FPGA pins # # Top Row (TR) # v # -------------------------------------------------- # | 119 118 117 116 115 114 113 112 GND 3v3 | # -------------------------------------------------- # # # Bottom Row (BR) # # v # ------------------------------------------------- # | 44 45 47 48 56 60 61 62 GND 3v3 | # ------------------------------------------------- # # -- Bottom Row # set_io --warn-no-port BR3 62 set_io --warn-no-port BR4 61 set_io --warn-no-port BR5 60 set_io --warn-no-port BR6 56 set_io --warn-no-port BR7 48 set_io --warn-no-port BR8 47 set_io --warn-no-port BR9 45 set_io --warn-no-port BR10 44 # -------------------------- SYSTEM CLOCK ------------------------------------ set_io --warn-no-port CLK 21