Add some comments.
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DDS.cpp
2
DDS.cpp
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@ -25,7 +25,7 @@ void DDS::start() {
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// clock as the DDS.
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// clock as the DDS.
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TCCR1B = _BV(CS11) | _BV(WGM13) | _BV(WGM12);
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TCCR1B = _BV(CS11) | _BV(WGM13) | _BV(WGM12);
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TCCR1A = 0;
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TCCR1A = 0;
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ICR1 = ((F_CPU / 8) / DDS_REFCLK_DEAULT) - 1;
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ICR1 = ((F_CPU / 8) / refclk) - 1;
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// Configure the ADC here to automatically run and be triggered off Timer1
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// Configure the ADC here to automatically run and be triggered off Timer1
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ADMUX = _BV(REFS0) | _BV(ADLAR) | 0; // Channel 0, shift result left (ADCH used)
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ADMUX = _BV(REFS0) | _BV(ADLAR) | 0; // Channel 0, shift result left (ADCH used)
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26
DDS.h
26
DDS.h
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@ -15,13 +15,26 @@
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// This leaves it floating in the centre of the PWM/DAC voltage range
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// This leaves it floating in the centre of the PWM/DAC voltage range
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#define DDS_IDLE_HIGH
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#define DDS_IDLE_HIGH
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// Select how fast the PWM is, at the expense of level accuracy.
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// A faster PWM rate will make for easier filtering of the output wave,
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// while a slower one will allow for more accurate voltage level outputs,
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// but will increase the filtering requirements on the output.
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// 8 = 62.5kHz PWM
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// 7 = 125kHz PWM
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// 6 = 250kHz PWM
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#define COMPARATOR_BITS 6
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#define COMPARATOR_BITS 6
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// This is how often we'll perform a phase advance, as well as ADC sampling
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// rate. The higher this value, the smoother the output wave will be, at the
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// expense of CPU time. It maxes out around 62000 (TBD)
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#define DDS_REFCLK_DEAULT 38400
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#define DDS_REFCLK_DEAULT 38400
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// When defined, use the 1024 element sine lookup table. This improves phase
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// accuracy, at the cost of more flash and CPU requirements.
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#define DDS_TABLE_LARGE
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#define DDS_TABLE_LARGE
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#ifdef DDS_TABLE_LARGE
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#ifdef DDS_TABLE_LARGE
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// How many bits to keep from the accumulator to look up in this table
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#define ACCUMULATOR_BIT_SHIFT (ACCUMULATOR_BITS-10)
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#define ACCUMULATOR_BIT_SHIFT (ACCUMULATOR_BITS-10)
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static const uint8_t ddsSineTable[1024] PROGMEM = {
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static const uint8_t ddsSineTable[1024] PROGMEM = {
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128,128,129,130,131,131,132,133,134,135,135,136,137,138,138,139,
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128,128,129,130,131,131,132,133,134,135,135,136,137,138,138,139,
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@ -115,11 +128,14 @@ class DDS {
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public:
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public:
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DDS(): refclk(DDS_REFCLK_DEAULT), accumulator(0), running(false) {};
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DDS(): refclk(DDS_REFCLK_DEAULT), accumulator(0), running(false) {};
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// Start all of the timers needed
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void start();
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void start();
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// Is the DDS presently producing a tone?
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const bool isRunning() { return running; };
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const bool isRunning() { return running; };
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// Stop the DDS timers
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void stop();
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void stop();
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// Start the PWM output, or stop it
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// Start and stop the PWM output
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void on() {
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void on() {
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timeLimited = false;
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timeLimited = false;
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running = true;
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running = true;
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@ -151,8 +167,13 @@ public:
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// frequency supported will fit in a short.
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// frequency supported will fit in a short.
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void setFrequency(unsigned short freq);
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void setFrequency(unsigned short freq);
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// Adjustable reference clock
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// Adjustable reference clock. This shoud be done before the timers are
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// started, or they will need to be restarted. Frequencies will need to
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// be set again to use the new clock.
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void setReferenceClock(unsigned long ref);
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void setReferenceClock(unsigned long ref);
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unsigned long getReferenceClock() {
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return refclk;
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}
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uint8_t getDutyCycle();
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uint8_t getDutyCycle();
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@ -162,6 +183,7 @@ public:
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amplitude = 8 - amp;
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amplitude = 8 - amp;
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}
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}
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// This is the function called by the ADC_vect ISR to produce the tones
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void clockTick();
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void clockTick();
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private:
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private:
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