split phy out into its own fileset (bell202)
This commit is contained in:
parent
ba97bd4702
commit
591796fb99
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@ -1,36 +1,46 @@
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#include <Arduino.h>
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#include "SimpleFIFO.h"
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#include "packet.h"
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#include "dds.h"
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#include "AX25.h"
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#include "bell202.h"
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#include <util/atomic.h>
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#define PHASE_BIT 8
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#define PHASE_INC 1
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#define PHASE_MAX (SAMPLEPERBIT * PHASE_BIT)
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#define PHASE_THRES (PHASE_MAX / 2)
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#define BIT_DIFFER(bitline1, bitline2) (((bitline1) ^ (bitline2)) & 0x01)
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#define EDGE_FOUND(bitline) BIT_DIFFER((bitline), (bitline) >> 1)
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#define PPOOL_SIZE 2
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#define AFSK_SPACE 2200
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#define AFSK_MARK 1200
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// Timers
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volatile unsigned long lastTx = 0;
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volatile unsigned long lastTxEnd = 0;
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volatile unsigned long lastRx = 0;
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#define T_BIT ((unsigned int)(SAMPLERATE/BITRATE))
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Bell202 afsk;
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#ifdef PACKET_PREALLOCATE
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SimpleFIFO<AFSK::Packet *,PPOOL_SIZE> preallocPool;
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AFSK::Packet preallocPackets[PPOOL_SIZE];
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SimpleFIFO<AX25::Packet *,PPOOL_SIZE> preallocPool;
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AX25::Packet preallocPackets[PPOOL_SIZE];
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#endif
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void AFSK::Encoder::process() {
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bool AX25::enabled() { return afsk.enabled(); }
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void AX25::start(DDS *d) { afsk.start(d); }
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// Determine what we want to do on this ADC tick.
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void AX25::timer() {
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static uint8_t tcnt = 0;
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if(++tcnt == T_BIT && afsk.isSending()) {
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PORTD |= _BV(6);
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// Only run the encoder every 8th tick
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// This is actually DDS RefClk / 1200 = 8, set as T_BIT
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// A different refclk needs a different value
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encoder.process();
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tcnt = 0;
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PORTD &= ~_BV(6);
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} else {
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decoder.process((int8_t)(ADCH - ADC_OFFSET));
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}
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}
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void AX25::Encoder::process() {
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// We're on the start of a byte position, so fetch one
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if(bitPosition == 0) {
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if(preamble) { // Still in preamble
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@ -105,20 +115,15 @@ void AFSK::Encoder::process() {
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// NRZI and AFSK uses toggling 0s, "no change" on 1
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// So, if not a 1, toggle to the opposite tone
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bool currentTone = afsk.encoderGetTone();
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if(!currentBit)
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currentTone = !currentTone;
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if(currentTone == 0) {
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PORTD |= _BV(7);
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dds->setFrequency(AFSK_SPACE);
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} else {
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PORTD &= ~_BV(7);
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dds->setFrequency(AFSK_MARK);
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}
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afsk.encoderSetTone(currentTone);
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}
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bool AFSK::Encoder::start() {
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if(!done || sending) {
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bool AX25::Encoder::start() {
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if(!done || afsk.isSending()) {
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return false;
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}
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@ -137,28 +142,26 @@ bool AFSK::Encoder::start() {
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packet = 0x0; // No initial packet, find in the ISR
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currentBytePos = 0;
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maxTx = 3;
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sending = true;
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nextByte = 0;
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dds->setFrequency(0);
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dds->on();
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afsk.encoderStart();
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return true;
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}
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void AFSK::Encoder::stop() {
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void AX25::Encoder::stop() {
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randomWait = 0;
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sending = false;
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done = true;
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dds->setFrequency(0);
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dds->off();
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afsk.encoderStop();
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}
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AFSK::Decoder::Decoder() {
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AX25::Decoder::Decoder() {
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// Initialize the sampler delay line (phase shift)
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//for(unsigned char i = 0; i < SAMPLEPERBIT/2; i++)
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// delay_fifo.enqueue(0);
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}
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bool AFSK::HDLCDecode::hdlcParse(bool bit, SimpleFIFO<uint8_t,AFSK_RX_FIFO_LEN> *fifo) {
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bool AX25::HDLCDecode::hdlcParse(bool bit, SimpleFIFO<uint8_t,AFSK_RX_FIFO_LEN> *fifo) {
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bool ret = true;
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demod_bits <<= 1;
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@ -205,70 +208,18 @@ bool AFSK::HDLCDecode::hdlcParse(bool bit, SimpleFIFO<uint8_t,AFSK_RX_FIFO_LEN>
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return ret;
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}
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template <typename T, int size>
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class FastRing {
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private:
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T ring[size];
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uint8_t position;
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public:
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FastRing(): position(0) {}
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inline void write(T value) {
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ring[(position++) & (size-1)] = value;
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}
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inline T read() const {
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return ring[position & (size-1)];
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}
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inline T readn(uint8_t n) const {
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return ring[(position + (~n+1)) & (size-1)];
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}
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};
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// Create a delay line that's half the length of the bit cycle (-90 degrees)
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FastRing<uint8_t,(T_BIT/2)> delayLine;
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// Handle the A/D converter interrupt (hopefully quickly :)
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void AFSK::Decoder::process(int8_t curr_sample) {
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// Run the same through the phase multiplier and butterworth filter
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iir_x[0] = iir_x[1];
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iir_x[1] = ((int8_t)delayLine.read() * curr_sample) >> 2;
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iir_y[0] = iir_y[1];
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iir_y[1] = iir_x[0] + iir_x[1] + (iir_y[0] >> 1) + (iir_y[0]>>3) + (iir_y[0]>>5);
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void AX25::Decoder::process(int8_t adc_val) {
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bool parse_ready = afsk.decoderProcess(adc_val);
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// Place this ADC sample into the delay line
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delayLine.write(curr_sample);
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// Shift the bit into place based on the output of the discriminator
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sampled_bits <<= 1;
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sampled_bits |= (iir_y[1] > 0) ? 1 : 0;
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// If we found a 0/1 transition, adjust phases to track
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if(EDGE_FOUND(sampled_bits)) {
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if(curr_phase < PHASE_THRES)
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curr_phase += PHASE_INC;
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else
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curr_phase -= PHASE_INC;
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}
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// Move ahead in phase
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curr_phase += PHASE_BIT;
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// If we've gone over the phase maximum, we should now have some data
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if(curr_phase >= PHASE_MAX) {
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curr_phase %= PHASE_MAX;
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found_bits <<= 1;
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// If we have 3 bits or more set, it's a positive bit
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register uint8_t bits = sampled_bits & 0x07;
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if(bits == 0x07 || bits == 0x06 || bits == 0x05 || bits == 0x03) {
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found_bits |= 1;
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}
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hdlc.hdlcParse(!EDGE_FOUND(found_bits), &rx_fifo); // Process it
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if (parse_ready) {
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hdlc.hdlcParse(!EDGE_FOUND(afsk.found_bits), &rx_fifo); // Process it
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}
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}
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// This routine uses a pre-allocated Packet structure
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// to save on the memory requirements of the stream data
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bool AFSK::Decoder::read() {
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bool AX25::Decoder::read() {
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bool retVal = false;
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if(!currentPacket) { // We failed a prior memory allocation
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currentPacket = pBuf.makePacket(PACKET_MAX_LEN);
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return retVal; // This is true if we parsed a packet in this flow
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}
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#define AFSK_ADC_INPUT 2
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void AFSK::Decoder::start() {
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void AX25::Decoder::start() {
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// Do this in start to allocate our first packet
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currentPacket = pBuf.makePacket(PACKET_MAX_LEN);
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/* ASSR &= ~(_BV(EXCLK) | _BV(AS2));
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// Do non-inverting PWM on pin OC2B (arduino pin 3) (p.159).
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// OC2A (arduino pin 11) stays in normal port operation:
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// COM2B1=1, COM2B0=0, COM2A1=0, COM2A0=0
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// Mode 1 - Phase correct PWM
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TCCR2A = (TCCR2A | _BV(COM2B1)) & ~(_BV(COM2B0) | _BV(COM2A1) | _BV(COM2A0)) |
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_BV(WGM21) | _BV(WGM20);
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// No prescaler (p.162)
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TCCR2B = (TCCR2B & ~(_BV(CS22) | _BV(CS21))) | _BV(CS20) | _BV(WGM22);
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OCR2A = pow(2,COMPARE_BITS)-1;
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OCR2B = 0;*/
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// This lets us use decoding functions that run at the same reference
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// clock as the DDS.
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// We use ICR1 as TOP and prescale by 8
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// Note that this requires the DDS to be started as well
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TCCR1A = 0;
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TCCR1B = _BV(CS11) | _BV(WGM13) | _BV(WGM12);
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ICR1 = ((F_CPU / 8) / 9600) - 1; //TODO: get the actual refclk from dds
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// NOTE: should divider be 1 or 8?
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ADMUX = _BV(REFS0) | _BV(ADLAR) | AFSK_ADC_INPUT; // Channel AFSK_ADC_INPUT, shift result left (ADCH used)
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DDRC &= ~_BV(AFSK_ADC_INPUT);
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PORTC &= ~_BV(AFSK_ADC_INPUT);
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DIDR0 |= _BV(AFSK_ADC_INPUT); // disable input buffer for ADC pin
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ADCSRB = _BV(ADTS2) | _BV(ADTS1) | _BV(ADTS0);
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ADCSRA = _BV(ADEN) | _BV(ADSC) | _BV(ADATE) | _BV(ADIE) | _BV(ADPS2); // | _BV(ADPS0);
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afsk.decoderStart();
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}
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AFSK::PacketBuffer::PacketBuffer() {
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AX25::PacketBuffer::PacketBuffer() {
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nextPacketIn = 0;
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nextPacketOut = 0;
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inBuffer = 0;
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#endif
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}
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unsigned char AFSK::PacketBuffer::readyCount() volatile {
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unsigned char AX25::PacketBuffer::readyCount() volatile {
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unsigned char i;
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unsigned int cnt = 0;
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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}
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// Return NULL on empty packet buffers
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AFSK::Packet *AFSK::PacketBuffer::getPacket() volatile {
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AX25::Packet *AX25::PacketBuffer::getPacket() volatile {
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unsigned char i = 0;
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AFSK::Packet *p = NULL;
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AX25::Packet *p = NULL;
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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if(inBuffer == 0) {
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}
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//void Packet::init(uint8_t *buf, unsigned int dlen, bool freeData) {
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void AFSK::Packet::init(unsigned short dlen) {
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void AX25::Packet::init(unsigned short dlen) {
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//data = (unsigned char *)buf;
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ready = 0;
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#ifdef PACKET_PREALLOCATE
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}
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// Allocate a new packet with a data buffer as set
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AFSK::Packet *AFSK::PacketBuffer::makePacket(unsigned short dlen) {
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AFSK::Packet *p;
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AX25::Packet *AX25::PacketBuffer::makePacket(unsigned short dlen) {
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AX25::Packet *p;
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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//Packet *p = findPooledPacket();
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#ifdef PACKET_PREALLOCATE
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}
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// Free a packet struct, mainly convenience
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void AFSK::PacketBuffer::freePacket(Packet *p) {
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void AX25::PacketBuffer::freePacket(Packet *p) {
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if(!p)
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return;
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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}
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// Put a packet onto the buffer array
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bool AFSK::PacketBuffer::putPacket(Packet *p) volatile {
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bool AX25::PacketBuffer::putPacket(Packet *p) volatile {
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ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
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if(inBuffer >= PACKET_BUFFER_SIZE) {
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return false;
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@ -508,11 +430,11 @@ bool AFSK::PacketBuffer::putPacket(Packet *p) volatile {
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}
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// Print a single byte to the data array
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size_t AFSK::Packet::write(uint8_t c) {
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size_t AX25::Packet::write(uint8_t c) {
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return (appendFCS(c)?1:0);
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}
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size_t AFSK::Packet::write(const uint8_t *ptr, size_t len) {
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size_t AX25::Packet::write(const uint8_t *ptr, size_t len) {
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size_t i;
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for(i = 0; i < len; ++i)
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if(!appendFCS(ptr[i]))
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// Add a callsign, flagged as source, destination, or digi
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// Also tell the routine the SSID to use and if this is the final callsign
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size_t AFSK::Packet::appendCallsign(const char *callsign, uint8_t ssid, bool final) {
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size_t AX25::Packet::appendCallsign(const char *callsign, uint8_t ssid, bool final) {
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uint8_t i;
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for(i = 0; i < strlen(callsign) && i < 6; i++) {
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appendFCS(callsign[i]<<1);
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#ifdef PACKET_PARSER
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// Process the AX25 frame and turn it into a bunch of useful strings
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bool AFSK::Packet::parsePacket() {
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bool AX25::Packet::parsePacket() {
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uint8_t *d = dataPtr;
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int i;
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}
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#endif
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void AFSK::Packet::printPacket(Stream *s) {
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void AX25::Packet::printPacket(Stream *s) {
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uint8_t i;
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#ifdef PACKET_PARSER
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if(!parsePacket()) {
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#endif
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}
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// Determine what we want to do on this ADC tick.
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void AFSK::timer() {
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static uint8_t tcnt = 0;
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if(++tcnt == T_BIT && encoder.isSending()) {
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PORTD |= _BV(6);
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// Only run the encoder every 8th tick
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// This is actually DDS RefClk / 1200 = 8, set as T_BIT
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// A different refclk needs a different value
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encoder.process();
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tcnt = 0;
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PORTD &= ~_BV(6);
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} else {
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//decoder.process(((int8_t)(ADCH - 128)));
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decoder.process((int8_t)(ADCH - 83));
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}
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}
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void AFSK::start(DDS *dds) {
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afskEnabled = true;
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encoder.setDDS(dds);
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decoder.start();
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}
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@ -0,0 +1,285 @@
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#ifndef _AX25_H_
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#define _AX25_H_
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#include <Arduino.h>
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#include <SimpleFIFO.h>
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#include <Bell202.h>
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#include <avr/pgmspace.h>
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#define RX_FIFO_LEN 16
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#define AFSK_RX_FIFO_LEN 16
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#define PACKET_BUFFER_SIZE 2
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#define PACKET_STATIC 0
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// Enable the packet parser which will tokenize the AX25 frame into easy strings
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#define PACKET_PARSER
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// If this is set, all the packet buffers will be pre-allocated at compile time
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// This will use more RAM, but can make it easier to do memory planning.
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// TODO: Make this actually work right and not crash.
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#define PACKET_PREALLOCATE
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// This is with all the digis, two addresses, and full payload
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// Dst(7) + Src(7) + Digis(56) + Ctl(1) + PID(1) + Data(0-256) + FCS(2)
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#define PACKET_MAX_LEN 330
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// Minimum is Dst + Src + Ctl + FCS
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#define AX25_PACKET_HEADER_MINLEN 17
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// HDLC framing bits
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#define HDLC_FRAME 0x7E
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#define HDLC_RESET 0x7F
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#define HDLC_PREAMBLE 0x00
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#define HDLC_ESCAPE 0x1B
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#define HDLC_TAIL 0x1C
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class AX25 {
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public:
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bool enabled();
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void start(DDS *d);
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void timer();
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class Packet:public Print {
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public:
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Packet():Print() {};
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virtual size_t write(uint8_t);
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// Stock virtual method does what we want here.
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//virtual size_t write(const char *);
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virtual size_t write(const uint8_t *, size_t);
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using Print::write;
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unsigned char ready : 1;
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unsigned char type : 2;
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unsigned char freeData : 1;
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unsigned short len;
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unsigned short maxLen;
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//void init(uint8_t *buf, unsigned int dlen, bool freeData);
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void init(unsigned short dlen);
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inline void free() {
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if(freeData)
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::free(dataPtr);
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}
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inline const unsigned char getByte(void) {
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return *readPos++;
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}
|
||||
inline const unsigned char getByte(uint16_t p) {
|
||||
return *(dataPtr+p);
|
||||
}
|
||||
inline void start() {
|
||||
fcs = 0xffff;
|
||||
// No longer put an explicit frame start here
|
||||
//*dataPos++ = HDLC_ESCAPE;
|
||||
//*dataPos++ = HDLC_FRAME;
|
||||
//len = 2;
|
||||
len = 0;
|
||||
}
|
||||
|
||||
inline bool append(char c) {
|
||||
if(len < maxLen) {
|
||||
++len;
|
||||
*dataPos++ = c;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
#define UPDATE_FCS(d) e=fcs^(d); f=e^(e<<4); fcs=(fcs>>8)^(f<<8)^(f<<3)^(f>>4)
|
||||
//#define UPDATE_FCS(d) s=(d)^(fcs>>8); t=s^(s>>4); fcs=(fcs<<8)^t^(t<<5)^(t<<12)
|
||||
inline bool appendFCS(unsigned char c) {
|
||||
register unsigned char e, f;
|
||||
if(len < maxLen - 4) { // Leave room for FCS/HDLC
|
||||
append(c);
|
||||
UPDATE_FCS(c);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
size_t appendCallsign(const char *callsign, uint8_t ssid, bool final = false);
|
||||
|
||||
inline void finish() {
|
||||
append(~(fcs & 0xff));
|
||||
append(~((fcs>>8) & 0xff));
|
||||
// No longer append the frame boundaries themselves
|
||||
//append(HDLC_ESCAPE);
|
||||
//append(HDLC_FRAME);
|
||||
ready = 1;
|
||||
}
|
||||
|
||||
inline void clear() {
|
||||
fcs = 0xffff;
|
||||
len = 0;
|
||||
readPos = dataPtr;
|
||||
dataPos = dataPtr;
|
||||
}
|
||||
|
||||
inline bool crcOK() {
|
||||
return (fcs == 0xF0B8);
|
||||
}
|
||||
#ifdef PACKET_PARSER
|
||||
bool parsePacket();
|
||||
#endif
|
||||
void printPacket(Stream *s);
|
||||
private:
|
||||
#ifdef PACKET_PREALLOCATE
|
||||
uint8_t dataPtr[PACKET_MAX_LEN]; // 256 byte I frame + headers max of 78
|
||||
#else
|
||||
uint8_t *dataPtr;
|
||||
#endif
|
||||
#ifdef PACKET_PARSER
|
||||
char srcCallsign[7];
|
||||
uint8_t srcSSID;
|
||||
char dstCallsign[7];
|
||||
uint8_t dstSSID;
|
||||
char digipeater[8][7];
|
||||
uint8_t digipeaterSSID[8];
|
||||
uint8_t *iFrameData;
|
||||
uint8_t length;
|
||||
uint8_t control;
|
||||
uint8_t pid;
|
||||
#endif
|
||||
uint8_t *dataPos, *readPos;
|
||||
unsigned short fcs;
|
||||
};
|
||||
|
||||
|
||||
class PacketBuffer {
|
||||
public:
|
||||
// Initialize the buffers
|
||||
PacketBuffer();
|
||||
// How many packets are in the buffer?
|
||||
unsigned char count() volatile { return inBuffer; };
|
||||
// And how many of those are ready?
|
||||
unsigned char readyCount() volatile;
|
||||
// Retrieve the next packet
|
||||
Packet *getPacket() volatile;
|
||||
// Create a packet structure as needed
|
||||
// This does not place it in the queue
|
||||
static Packet *makePacket(unsigned short);
|
||||
// Conveniently free packet memory
|
||||
static void freePacket(Packet *);
|
||||
// Place a packet into the buffer
|
||||
bool putPacket(Packet *) volatile;
|
||||
private:
|
||||
volatile unsigned char inBuffer;
|
||||
Packet * volatile packets[PACKET_BUFFER_SIZE];
|
||||
volatile unsigned char nextPacketIn;
|
||||
volatile unsigned char nextPacketOut;
|
||||
};
|
||||
|
||||
class Encoder {
|
||||
public:
|
||||
Encoder() {
|
||||
randomWait = 1000; // At the very begin, wait at least one second
|
||||
done = true;
|
||||
packet = 0x0;
|
||||
currentBytePos = 0;
|
||||
nextByte = 0;
|
||||
}
|
||||
void setDDS(DDS *d) { dds = d; }
|
||||
//int16 getReferenceClock() { return dds.getReferenceClock(); }
|
||||
volatile inline bool isDone() volatile {
|
||||
return done;
|
||||
}
|
||||
volatile inline bool hasPackets() volatile {
|
||||
return (pBuf.count() > 0);
|
||||
}
|
||||
inline bool putPacket(Packet *packet) {
|
||||
return pBuf.putPacket(packet);
|
||||
}
|
||||
inline void setRandomWait() {
|
||||
randomWait = 250 + (rand() % 1000) + millis();
|
||||
}
|
||||
bool start();
|
||||
void stop();
|
||||
void process();
|
||||
private:
|
||||
byte currentByte;
|
||||
byte currentBit : 1;
|
||||
byte lastZero : 3;
|
||||
byte bitPosition : 3;
|
||||
byte preamble : 6;
|
||||
//byte bitClock;
|
||||
bool hdlc;
|
||||
byte nextByte;
|
||||
byte maxTx;
|
||||
Packet *packet;
|
||||
PacketBuffer pBuf;
|
||||
unsigned int currentBytePos;
|
||||
volatile unsigned long randomWait;
|
||||
volatile bool done;
|
||||
DDS *dds;
|
||||
};
|
||||
|
||||
class HDLCDecode {
|
||||
public:
|
||||
bool hdlcParse(bool, SimpleFIFO<uint8_t,RX_FIFO_LEN> *fifo);
|
||||
volatile bool rxstart;
|
||||
private:
|
||||
uint8_t demod_bits;
|
||||
uint8_t bit_idx;
|
||||
uint8_t currchar;
|
||||
};
|
||||
|
||||
class Decoder {
|
||||
public:
|
||||
Decoder();
|
||||
void start();
|
||||
bool read();
|
||||
void process(int8_t);
|
||||
inline bool dataAvailable() {
|
||||
return (rx_fifo.count() > 0);
|
||||
}
|
||||
inline uint8_t getByte() {
|
||||
return rx_fifo.dequeue();
|
||||
}
|
||||
inline uint8_t packetCount() volatile {
|
||||
return pBuf.count();
|
||||
}
|
||||
inline Packet *getPacket() {
|
||||
return pBuf.getPacket();
|
||||
}
|
||||
inline bool isReceiving() volatile {
|
||||
return hdlc.rxstart;
|
||||
}
|
||||
private:
|
||||
Packet *currentPacket;
|
||||
SimpleFIFO<uint8_t,RX_FIFO_LEN> rx_fifo; // This should be drained fairly often
|
||||
PacketBuffer pBuf;
|
||||
HDLCDecode hdlc;
|
||||
};
|
||||
|
||||
public:
|
||||
inline bool read() {
|
||||
return decoder.read();
|
||||
}
|
||||
volatile inline bool txReady() volatile {
|
||||
if(encoder.isDone() && encoder.hasPackets())
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
volatile inline bool isDone() volatile { return encoder.isDone(); }
|
||||
inline bool txStart() {
|
||||
if(decoder.isReceiving()) {
|
||||
encoder.setRandomWait();
|
||||
return false;
|
||||
}
|
||||
return encoder.start();
|
||||
}
|
||||
inline bool putTXPacket(Packet *packet) {
|
||||
bool ret = encoder.putPacket(packet);
|
||||
if(!ret) // No room?
|
||||
PacketBuffer::freePacket(packet);
|
||||
return ret;
|
||||
}
|
||||
inline Packet *getRXPacket() {
|
||||
return decoder.getPacket();
|
||||
}
|
||||
inline uint8_t rxPacketCount() volatile {
|
||||
return decoder.packetCount();
|
||||
}
|
||||
//unsigned long lastTx;
|
||||
//unsigned long lastRx;
|
||||
Encoder encoder;
|
||||
Decoder decoder;
|
||||
};
|
||||
#endif /* _AX25_H_ */
|
24
src/KISS.cpp
24
src/KISS.cpp
|
@ -1,8 +1,8 @@
|
|||
#include <HamShield.h>
|
||||
#include "packet.h"
|
||||
#include "AX25.h"
|
||||
#include "KISS.h"
|
||||
|
||||
//AFSK::Packet kissPacket;
|
||||
//AX25::Packet kissPacket;
|
||||
bool inFrame = false;
|
||||
uint8_t kissBuffer[PACKET_MAX_LEN];
|
||||
uint16_t kissLen = 0;
|
||||
|
@ -11,14 +11,14 @@ uint16_t kissLen = 0;
|
|||
// KISS equipment, and look if we have anything to relay along
|
||||
void KISS::loop() {
|
||||
static bool currentlySending = false;
|
||||
if(afsk->decoder.read() || afsk->rxPacketCount()) {
|
||||
if(ax25->decoder.read() || ax25->rxPacketCount()) {
|
||||
// A true return means something was put onto the packet FIFO
|
||||
// If we actually have data packets in the buffer, process them all now
|
||||
while(afsk->rxPacketCount()) {
|
||||
AFSK::Packet *packet = afsk->getRXPacket();
|
||||
while(ax25->rxPacketCount()) {
|
||||
AX25::Packet *packet = ax25->getRXPacket();
|
||||
if(packet) {
|
||||
writePacket(packet);
|
||||
AFSK::PacketBuffer::freePacket(packet);
|
||||
AX25::PacketBuffer::freePacket(packet);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -28,13 +28,13 @@ void KISS::loop() {
|
|||
if(c == KISS_FEND) {
|
||||
if(inFrame && kissLen > 0) {
|
||||
int i;
|
||||
AFSK::Packet *packet = AFSK::PacketBuffer::makePacket(PACKET_MAX_LEN);
|
||||
AX25::Packet *packet = AX25::PacketBuffer::makePacket(PACKET_MAX_LEN);
|
||||
packet->start();
|
||||
for(i = 0; i < kissLen; i++) {
|
||||
packet->appendFCS(kissBuffer[i]);
|
||||
}
|
||||
packet->finish();
|
||||
afsk->encoder.putPacket(packet);
|
||||
ax25->encoder.putPacket(packet);
|
||||
}
|
||||
kissLen = 0;
|
||||
inFrame = false;
|
||||
|
@ -57,21 +57,21 @@ void KISS::loop() {
|
|||
inFrame = true;
|
||||
}
|
||||
}
|
||||
if(afsk->txReady()) {
|
||||
if(ax25->txReady()) {
|
||||
radio->setModeTransmit();
|
||||
currentlySending = true;
|
||||
if(!afsk->txStart()) { // Unable to start for some reason
|
||||
if(!ax25->txStart()) { // Unable to start for some reason
|
||||
radio->setModeReceive();
|
||||
currentlySending = false;
|
||||
}
|
||||
}
|
||||
if(currentlySending && afsk->encoder.isDone()) {
|
||||
if(currentlySending && ax25->encoder.isDone()) {
|
||||
radio->setModeReceive();
|
||||
currentlySending = false;
|
||||
}
|
||||
}
|
||||
|
||||
void KISS::writePacket(AFSK::Packet *p) {
|
||||
void KISS::writePacket(AX25::Packet *p) {
|
||||
int i;
|
||||
io->write(KISS_FEND);
|
||||
io->write((uint8_t)0); // Host to TNC port identifier
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
#define _KISS_H_
|
||||
|
||||
#include <HamShield.h>
|
||||
#include "packet.h"
|
||||
#include "AX25.h"
|
||||
|
||||
#define KISS_FEND 0xC0
|
||||
#define KISS_FESC 0xDB
|
||||
|
@ -11,15 +11,15 @@
|
|||
|
||||
class KISS {
|
||||
public:
|
||||
KISS(Stream *_io, HamShield *h, DDS *d, AFSK *a) : io(_io), radio(h), dds(d), afsk(a) {}
|
||||
KISS(Stream *_io, HamShield *h, DDS *d, AX25 *a) : io(_io), radio(h), dds(d), ax25(a) {}
|
||||
bool read();
|
||||
void writePacket(AFSK::Packet *);
|
||||
void writePacket(AX25::Packet *);
|
||||
void loop();
|
||||
private:
|
||||
Stream *io;
|
||||
HamShield *radio;
|
||||
DDS *dds;
|
||||
AFSK *afsk;
|
||||
AX25 *ax25;
|
||||
};
|
||||
|
||||
#endif /* _KISS_H_ */
|
||||
|
|
|
@ -0,0 +1,132 @@
|
|||
#include <Arduino.h>
|
||||
#include "dds.h"
|
||||
#include "bell202.h"
|
||||
|
||||
|
||||
#define T_BIT ((unsigned int)(SAMPLERATE/BITRATE))
|
||||
|
||||
bool Bell202::encoderStart() {
|
||||
sending = true;
|
||||
dds->setFrequency(0);
|
||||
dds->on();
|
||||
return true;
|
||||
}
|
||||
void Bell202::encoderStop() {
|
||||
sending = false;
|
||||
dds->setFrequency(0);
|
||||
dds->off();
|
||||
}
|
||||
|
||||
void Bell202::encoderSetTone(bool tone) {
|
||||
currentTone = tone;
|
||||
if(tone == 0) {
|
||||
PORTD |= _BV(7);
|
||||
dds->setFrequency(AFSK_SPACE);
|
||||
} else {
|
||||
PORTD &= ~_BV(7);
|
||||
dds->setFrequency(AFSK_MARK);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename T, int size>
|
||||
class FastRing {
|
||||
private:
|
||||
T ring[size];
|
||||
uint8_t position;
|
||||
public:
|
||||
FastRing(): position(0) {}
|
||||
inline void write(T value) {
|
||||
ring[(position++) & (size-1)] = value;
|
||||
}
|
||||
inline T read() const {
|
||||
return ring[position & (size-1)];
|
||||
}
|
||||
inline T readn(uint8_t n) const {
|
||||
return ring[(position + (~n+1)) & (size-1)];
|
||||
}
|
||||
};
|
||||
// Create a delay line that's half the length of the bit cycle (-90 degrees)
|
||||
FastRing<uint8_t,(T_BIT/2)> delayLine;
|
||||
|
||||
// Handle the A/D converter interrupt (hopefully quickly :)
|
||||
bool Bell202::decoderProcess(int8_t curr_sample) {
|
||||
// Run the same through the phase multiplier and butterworth filter
|
||||
iir_x[0] = iir_x[1];
|
||||
iir_x[1] = ((int8_t)delayLine.read() * curr_sample) >> 2;
|
||||
iir_y[0] = iir_y[1];
|
||||
iir_y[1] = iir_x[0] + iir_x[1] + (iir_y[0] >> 1) + (iir_y[0]>>3) + (iir_y[0]>>5);
|
||||
|
||||
// Place this ADC sample into the delay line
|
||||
delayLine.write(curr_sample);
|
||||
|
||||
// Shift the bit into place based on the output of the discriminator
|
||||
sampled_bits <<= 1;
|
||||
sampled_bits |= (iir_y[1] > 0) ? 1 : 0;
|
||||
|
||||
// If we found a 0/1 transition, adjust phases to track
|
||||
if(EDGE_FOUND(sampled_bits)) {
|
||||
if(curr_phase < PHASE_THRES)
|
||||
curr_phase += PHASE_INC;
|
||||
else
|
||||
curr_phase -= PHASE_INC;
|
||||
}
|
||||
|
||||
// Move ahead in phase
|
||||
curr_phase += PHASE_BIT;
|
||||
|
||||
// If we've gone over the phase maximum, we should now have some data
|
||||
if(curr_phase >= PHASE_MAX) {
|
||||
curr_phase %= PHASE_MAX;
|
||||
found_bits <<= 1;
|
||||
|
||||
// If we have 3 bits or more set, it's a positive bit
|
||||
register uint8_t bits = sampled_bits & 0x07;
|
||||
if(bits == 0x07 || bits == 0x06 || bits == 0x05 || bits == 0x03) {
|
||||
found_bits |= 1;
|
||||
}
|
||||
|
||||
// pass back to encoder
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
#define AFSK_ADC_INPUT 2
|
||||
void Bell202::decoderStart() {
|
||||
/* ASSR &= ~(_BV(EXCLK) | _BV(AS2));
|
||||
|
||||
// Do non-inverting PWM on pin OC2B (arduino pin 3) (p.159).
|
||||
// OC2A (arduino pin 11) stays in normal port operation:
|
||||
// COM2B1=1, COM2B0=0, COM2A1=0, COM2A0=0
|
||||
// Mode 1 - Phase correct PWM
|
||||
TCCR2A = (TCCR2A | _BV(COM2B1)) & ~(_BV(COM2B0) | _BV(COM2A1) | _BV(COM2A0)) |
|
||||
_BV(WGM21) | _BV(WGM20);
|
||||
// No prescaler (p.162)
|
||||
TCCR2B = (TCCR2B & ~(_BV(CS22) | _BV(CS21))) | _BV(CS20) | _BV(WGM22);
|
||||
|
||||
OCR2A = pow(2,COMPARE_BITS)-1;
|
||||
OCR2B = 0;*/
|
||||
|
||||
|
||||
// This lets us use decoding functions that run at the same reference
|
||||
// clock as the DDS.
|
||||
// We use ICR1 as TOP and prescale by 8
|
||||
// Note that this requires the DDS to be started as well
|
||||
TCCR1A = 0;
|
||||
TCCR1B = _BV(CS11) | _BV(WGM13) | _BV(WGM12);
|
||||
ICR1 = ((F_CPU / 8) / 9600) - 1; //TODO: get the actual refclk from dds
|
||||
// NOTE: should divider be 1 or 8?
|
||||
ADMUX = _BV(REFS0) | _BV(ADLAR) | AFSK_ADC_INPUT; // Channel AFSK_ADC_INPUT, shift result left (ADCH used)
|
||||
DDRC &= ~_BV(AFSK_ADC_INPUT);
|
||||
PORTC &= ~_BV(AFSK_ADC_INPUT);
|
||||
DIDR0 |= _BV(AFSK_ADC_INPUT); // disable input buffer for ADC pin
|
||||
ADCSRB = _BV(ADTS2) | _BV(ADTS1) | _BV(ADTS0);
|
||||
ADCSRA = _BV(ADEN) | _BV(ADSC) | _BV(ADATE) | _BV(ADIE) | _BV(ADPS2); // | _BV(ADPS0);
|
||||
}
|
||||
|
||||
void Bell202::start(DDS *dds) {
|
||||
afskEnabled = true;
|
||||
encoderSetDDS(dds);
|
||||
decoderStart();
|
||||
}
|
|
@ -0,0 +1,83 @@
|
|||
#ifndef _BELL202_H_
|
||||
#define _BELL202_H_
|
||||
|
||||
/*
|
||||
* bell202.h
|
||||
* The Bell202 class implements an AFSK transceiver at the bit level.
|
||||
* All encoding and framing should be done at a higher level (e.g. HDLC and AX.25)
|
||||
*
|
||||
* See http://destevez.net/2016/06/kiss-hdlc-ax-25-and-friends/
|
||||
*/
|
||||
|
||||
#include <Arduino.h>
|
||||
#include <DDS.h>
|
||||
#include <avr/pgmspace.h>
|
||||
|
||||
#define SAMPLERATE 9600
|
||||
#define BITRATE 1200
|
||||
|
||||
#define SAMPLEPERBIT (SAMPLERATE / BITRATE)
|
||||
|
||||
#define RX_FIFO_LEN 16
|
||||
|
||||
#define AFSK_RX_FIFO_LEN 16
|
||||
|
||||
#define BIT_DIFFER(bitline1, bitline2) (((bitline1) ^ (bitline2)) & 0x01)
|
||||
|
||||
#define EDGE_FOUND(bitline) BIT_DIFFER((bitline), (bitline) >> 1)
|
||||
|
||||
#define T_BIT ((unsigned int)(SAMPLERATE/BITRATE))
|
||||
|
||||
#define PHASE_BIT 8
|
||||
#define PHASE_INC 1
|
||||
|
||||
#define PHASE_MAX (SAMPLEPERBIT * PHASE_BIT)
|
||||
#define PHASE_THRES (PHASE_MAX / 2)
|
||||
|
||||
#define AFSK_SPACE 2200
|
||||
#define AFSK_MARK 1200
|
||||
|
||||
#define ADC_OFFSET 83
|
||||
|
||||
class Bell202 {
|
||||
private:
|
||||
volatile bool afskEnabled;
|
||||
public:
|
||||
Bell202() {
|
||||
sending = false;
|
||||
}
|
||||
volatile inline bool enabled() { return afskEnabled; }
|
||||
volatile inline bool isSending() volatile {
|
||||
return sending;
|
||||
}
|
||||
|
||||
void encoderSetDDS(DDS *d) { dds = d; }
|
||||
//int16 getReferenceClock() { return dds.getReferenceClock(); }
|
||||
bool encoderStart();
|
||||
void encoderStop();
|
||||
void encoderSetTone(bool tone);
|
||||
bool encoderGetTone() { return currentTone; }
|
||||
|
||||
void decoderStart();
|
||||
bool decoderRead();
|
||||
bool decoderProcess(int8_t);
|
||||
|
||||
void start(DDS *);
|
||||
|
||||
uint8_t found_bits;
|
||||
|
||||
private:
|
||||
volatile bool sending;
|
||||
byte currentTone : 1;
|
||||
//byte bitClock;
|
||||
DDS *dds;
|
||||
|
||||
int16_t iir_x[2];
|
||||
int16_t iir_y[2];
|
||||
int8_t curr_phase;
|
||||
uint8_t sampled_bits;
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif /* _BELL202_H_ */
|
307
src/packet.h
307
src/packet.h
|
@ -1,304 +1,9 @@
|
|||
#ifndef _AFSK_H_
|
||||
#define _AFSK_H_
|
||||
#ifndef _PACKET_H_
|
||||
#define _PACKET_H_
|
||||
|
||||
#include <Arduino.h>
|
||||
#include <SimpleFIFO.h>
|
||||
#include <DDS.h>
|
||||
#include <avr/pgmspace.h>
|
||||
#include "AX25.h"
|
||||
#include "bell202.h"
|
||||
|
||||
#define SAMPLERATE 9600
|
||||
#define BITRATE 1200
|
||||
#define AFSK AX25 //
|
||||
|
||||
#define SAMPLEPERBIT (SAMPLERATE / BITRATE)
|
||||
|
||||
#define RX_FIFO_LEN 16
|
||||
|
||||
#define AFSK_RX_FIFO_LEN 16
|
||||
#define PACKET_BUFFER_SIZE 2
|
||||
#define PACKET_STATIC 0
|
||||
|
||||
// Enable the packet parser which will tokenize the AX25 frame into easy strings
|
||||
#define PACKET_PARSER
|
||||
|
||||
// If this is set, all the packet buffers will be pre-allocated at compile time
|
||||
// This will use more RAM, but can make it easier to do memory planning.
|
||||
// TODO: Make this actually work right and not crash.
|
||||
#define PACKET_PREALLOCATE
|
||||
|
||||
// This is with all the digis, two addresses, and full payload
|
||||
// Dst(7) + Src(7) + Digis(56) + Ctl(1) + PID(1) + Data(0-256) + FCS(2)
|
||||
#define PACKET_MAX_LEN 330
|
||||
// Minimum is Dst + Src + Ctl + FCS
|
||||
#define AX25_PACKET_HEADER_MINLEN 17
|
||||
|
||||
// HDLC framing bits
|
||||
#define HDLC_FRAME 0x7E
|
||||
#define HDLC_RESET 0x7F
|
||||
#define HDLC_PREAMBLE 0x00
|
||||
#define HDLC_ESCAPE 0x1B
|
||||
#define HDLC_TAIL 0x1C
|
||||
|
||||
class AFSK {
|
||||
private:
|
||||
volatile bool afskEnabled;
|
||||
public:
|
||||
bool enabled() { return afskEnabled; };
|
||||
|
||||
class Packet:public Print {
|
||||
public:
|
||||
Packet():Print() {};
|
||||
virtual size_t write(uint8_t);
|
||||
// Stock virtual method does what we want here.
|
||||
//virtual size_t write(const char *);
|
||||
virtual size_t write(const uint8_t *, size_t);
|
||||
using Print::write;
|
||||
unsigned char ready : 1;
|
||||
unsigned char type : 2;
|
||||
unsigned char freeData : 1;
|
||||
unsigned short len;
|
||||
unsigned short maxLen;
|
||||
//void init(uint8_t *buf, unsigned int dlen, bool freeData);
|
||||
void init(unsigned short dlen);
|
||||
inline void free() {
|
||||
if(freeData)
|
||||
::free(dataPtr);
|
||||
}
|
||||
inline const unsigned char getByte(void) {
|
||||
return *readPos++;
|
||||
}
|
||||
inline const unsigned char getByte(uint16_t p) {
|
||||
return *(dataPtr+p);
|
||||
}
|
||||
inline void start() {
|
||||
fcs = 0xffff;
|
||||
// No longer put an explicit frame start here
|
||||
//*dataPos++ = HDLC_ESCAPE;
|
||||
//*dataPos++ = HDLC_FRAME;
|
||||
//len = 2;
|
||||
len = 0;
|
||||
}
|
||||
|
||||
inline bool append(char c) {
|
||||
if(len < maxLen) {
|
||||
++len;
|
||||
*dataPos++ = c;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
#define UPDATE_FCS(d) e=fcs^(d); f=e^(e<<4); fcs=(fcs>>8)^(f<<8)^(f<<3)^(f>>4)
|
||||
//#define UPDATE_FCS(d) s=(d)^(fcs>>8); t=s^(s>>4); fcs=(fcs<<8)^t^(t<<5)^(t<<12)
|
||||
inline bool appendFCS(unsigned char c) {
|
||||
register unsigned char e, f;
|
||||
if(len < maxLen - 4) { // Leave room for FCS/HDLC
|
||||
append(c);
|
||||
UPDATE_FCS(c);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
size_t appendCallsign(const char *callsign, uint8_t ssid, bool final = false);
|
||||
|
||||
inline void finish() {
|
||||
append(~(fcs & 0xff));
|
||||
append(~((fcs>>8) & 0xff));
|
||||
// No longer append the frame boundaries themselves
|
||||
//append(HDLC_ESCAPE);
|
||||
//append(HDLC_FRAME);
|
||||
ready = 1;
|
||||
}
|
||||
|
||||
inline void clear() {
|
||||
fcs = 0xffff;
|
||||
len = 0;
|
||||
readPos = dataPtr;
|
||||
dataPos = dataPtr;
|
||||
}
|
||||
|
||||
inline bool crcOK() {
|
||||
return (fcs == 0xF0B8);
|
||||
}
|
||||
#ifdef PACKET_PARSER
|
||||
bool parsePacket();
|
||||
#endif
|
||||
void printPacket(Stream *s);
|
||||
private:
|
||||
#ifdef PACKET_PREALLOCATE
|
||||
uint8_t dataPtr[PACKET_MAX_LEN]; // 256 byte I frame + headers max of 78
|
||||
#else
|
||||
uint8_t *dataPtr;
|
||||
#endif
|
||||
#ifdef PACKET_PARSER
|
||||
char srcCallsign[7];
|
||||
uint8_t srcSSID;
|
||||
char dstCallsign[7];
|
||||
uint8_t dstSSID;
|
||||
char digipeater[8][7];
|
||||
uint8_t digipeaterSSID[8];
|
||||
uint8_t *iFrameData;
|
||||
uint8_t length;
|
||||
uint8_t control;
|
||||
uint8_t pid;
|
||||
#endif
|
||||
uint8_t *dataPos, *readPos;
|
||||
unsigned short fcs;
|
||||
};
|
||||
|
||||
|
||||
class PacketBuffer {
|
||||
public:
|
||||
// Initialize the buffers
|
||||
PacketBuffer();
|
||||
// How many packets are in the buffer?
|
||||
unsigned char count() volatile { return inBuffer; };
|
||||
// And how many of those are ready?
|
||||
unsigned char readyCount() volatile;
|
||||
// Retrieve the next packet
|
||||
Packet *getPacket() volatile;
|
||||
// Create a packet structure as needed
|
||||
// This does not place it in the queue
|
||||
static Packet *makePacket(unsigned short);
|
||||
// Conveniently free packet memory
|
||||
static void freePacket(Packet *);
|
||||
// Place a packet into the buffer
|
||||
bool putPacket(Packet *) volatile;
|
||||
private:
|
||||
volatile unsigned char inBuffer;
|
||||
Packet * volatile packets[PACKET_BUFFER_SIZE];
|
||||
volatile unsigned char nextPacketIn;
|
||||
volatile unsigned char nextPacketOut;
|
||||
};
|
||||
|
||||
class Encoder {
|
||||
public:
|
||||
Encoder() {
|
||||
randomWait = 1000; // At the very begin, wait at least one second
|
||||
sending = false;
|
||||
done = true;
|
||||
packet = 0x0;
|
||||
currentBytePos = 0;
|
||||
nextByte = 0;
|
||||
}
|
||||
void setDDS(DDS *d) { dds = d; }
|
||||
//int16 getReferenceClock() { return dds.getReferenceClock(); }
|
||||
volatile inline bool isSending() volatile {
|
||||
return sending;
|
||||
}
|
||||
volatile inline bool isDone() volatile {
|
||||
return done;
|
||||
}
|
||||
volatile inline bool hasPackets() volatile {
|
||||
return (pBuf.count() > 0);
|
||||
}
|
||||
inline bool putPacket(Packet *packet) {
|
||||
return pBuf.putPacket(packet);
|
||||
}
|
||||
inline void setRandomWait() {
|
||||
randomWait = 250 + (rand() % 1000) + millis();
|
||||
}
|
||||
bool start();
|
||||
void stop();
|
||||
void process();
|
||||
private:
|
||||
volatile bool sending;
|
||||
byte currentByte;
|
||||
byte currentBit : 1;
|
||||
byte currentTone : 1;
|
||||
byte lastZero : 3;
|
||||
byte bitPosition : 3;
|
||||
byte preamble : 6;
|
||||
//byte bitClock;
|
||||
bool hdlc;
|
||||
byte nextByte;
|
||||
byte maxTx;
|
||||
Packet *packet;
|
||||
PacketBuffer pBuf;
|
||||
unsigned int currentBytePos;
|
||||
volatile unsigned long randomWait;
|
||||
volatile bool done;
|
||||
DDS *dds;
|
||||
};
|
||||
|
||||
class HDLCDecode {
|
||||
public:
|
||||
bool hdlcParse(bool, SimpleFIFO<uint8_t,RX_FIFO_LEN> *fifo);
|
||||
volatile bool rxstart;
|
||||
private:
|
||||
uint8_t demod_bits;
|
||||
uint8_t bit_idx;
|
||||
uint8_t currchar;
|
||||
};
|
||||
|
||||
class Decoder {
|
||||
public:
|
||||
Decoder();
|
||||
void start();
|
||||
bool read();
|
||||
void process(int8_t);
|
||||
inline bool dataAvailable() {
|
||||
return (rx_fifo.count() > 0);
|
||||
}
|
||||
inline uint8_t getByte() {
|
||||
return rx_fifo.dequeue();
|
||||
}
|
||||
inline uint8_t packetCount() volatile {
|
||||
return pBuf.count();
|
||||
}
|
||||
inline Packet *getPacket() {
|
||||
return pBuf.getPacket();
|
||||
}
|
||||
inline bool isReceiving() volatile {
|
||||
return hdlc.rxstart;
|
||||
}
|
||||
private:
|
||||
Packet *currentPacket;
|
||||
//SimpleFIFO<int8_t,SAMPLEPERBIT/2+1> delay_fifo;
|
||||
SimpleFIFO<uint8_t,RX_FIFO_LEN> rx_fifo; // This should be drained fairly often
|
||||
int16_t iir_x[2];
|
||||
int16_t iir_y[2];
|
||||
uint8_t sampled_bits;
|
||||
int8_t curr_phase;
|
||||
uint8_t found_bits;
|
||||
PacketBuffer pBuf;
|
||||
HDLCDecode hdlc;
|
||||
};
|
||||
|
||||
public:
|
||||
inline bool read() {
|
||||
return decoder.read();
|
||||
}
|
||||
volatile inline bool txReady() volatile {
|
||||
if(encoder.isDone() && encoder.hasPackets())
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
volatile inline bool isDone() volatile { return encoder.isDone(); }
|
||||
inline bool txStart() {
|
||||
if(decoder.isReceiving()) {
|
||||
encoder.setRandomWait();
|
||||
return false;
|
||||
}
|
||||
return encoder.start();
|
||||
}
|
||||
inline bool putTXPacket(Packet *packet) {
|
||||
bool ret = encoder.putPacket(packet);
|
||||
if(!ret) // No room?
|
||||
PacketBuffer::freePacket(packet);
|
||||
return ret;
|
||||
}
|
||||
inline Packet *getRXPacket() {
|
||||
return decoder.getPacket();
|
||||
}
|
||||
inline uint8_t rxPacketCount() volatile {
|
||||
return decoder.packetCount();
|
||||
}
|
||||
//unsigned long lastTx;
|
||||
//unsigned long lastRx;
|
||||
void start(DDS *);
|
||||
void timer();
|
||||
Encoder encoder;
|
||||
Decoder decoder;
|
||||
};
|
||||
#endif /* _AFSK_H_ */
|
||||
#endif /* _PACKET_H_ */
|
Loading…
Reference in New Issue