143 lines
3.9 KiB
Plaintext
143 lines
3.9 KiB
Plaintext
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# -----------------------------------------------------------------------------
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#- Icestick constraint file (.pcf)
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#- By Juan Gonzalez (Obijuan)
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#- April - 2016
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#- GPL license
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# -----------------------------------------------------------------------------
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# -- Pinout: http://www.pighixxx.com/test/2016/02/icestick-pinout/
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# -- Guide: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/icestickusermanual.pdf
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# -- Icestick leds map
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#
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# D1
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# D4 D5 D2
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# D3
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#
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# -- D1-D4: Red leds
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# -- D5: green led
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# ------------ Red leds ------------------------------------------------------
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set_io --warn-no-port D1 99
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set_io --warn-no-port D2 98
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set_io --warn-no-port D3 97
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set_io --warn-no-port D4 96
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# ------------ Green led -----------------------------------------------------
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set_io --warn-no-port D5 95
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# ------------ IrDA ----------------------------------------------------------
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set_io --warn-no-port IrDA_TX 105
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set_io --warn-no-port IrDA_RX 106
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#-- SD = 0, enable IrDA
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set_io --warn-no-port SD 107
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# ------------ PMOD connector ------------------------------------------------
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#
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# Pmod standar numeration (Oriented according the icestick, with the
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# usb connector pointing to the left and IRda to the right)
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#
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# --------
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# | 12 6 |
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# | 11 5 |
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# | 10 4 |
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# | 9 3 |
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# | 8 2 |
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# | 7 1 | <
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# --------
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#
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# FPGA pins:
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#
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# ----------
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# | 3V3 3V3 |
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# | GND GND |
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# | 91 81 |
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# | 90 80 |
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# | 88 79 |
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# | 87 78 | <
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# ----------
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#
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set_io --warn-no-port PMOD1 78
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set_io --warn-no-port PMOD2 79
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set_io --warn-no-port PMOD3 80
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set_io --warn-no-port PMOD4 81
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set_io --warn-no-port PMOD7 87
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set_io --warn-no-port PMOD8 88
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set_io --warn-no-port PMOD9 90
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set_io --warn-no-port PMOD10 91
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# ------------------------ EXPANSION I/O ------------------------------------
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#
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# -- Numeration
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#
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# Top Row (TR):
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# v
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# --------------------------------
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# | 10 9 8 7 6 5 4 3 2 1 |
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# --------------------------------
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#
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# Bottom Row (BR):
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#
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# v
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# --------------------------------
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# | 10 9 8 7 6 5 4 3 2 1 |
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# --------------------------------
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#
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# --- FPGA pins
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#
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# Top Row (TR)
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# v
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# --------------------------------------------------
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# | 119 118 117 116 115 114 113 112 GND 3v3 |
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# --------------------------------------------------
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#
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#
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# Bottom Row (BR)
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#
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# v
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# -------------------------------------------------
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# | 44 45 47 48 56 60 61 62 GND 3v3 |
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# -------------------------------------------------
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#
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# -- Top Row
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set_io --warn-no-port TR3 112
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set_io --warn-no-port TR4 113
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set_io --warn-no-port TR5 114
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set_io --warn-no-port TR6 115
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set_io --warn-no-port TR7 116
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set_io --warn-no-port TR8 117
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set_io --warn-no-port TR9 118
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set_io --warn-no-port TR10 119
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#
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# -- Bottom Row
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set_io --warn-no-port BR3 62
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set_io --warn-no-port BR4 61
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set_io --warn-no-port BR5 60
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set_io --warn-no-port BR6 56
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set_io --warn-no-port BR7 48
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set_io --warn-no-port BR8 47
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set_io --warn-no-port BR9 45
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set_io --warn-no-port BR10 44
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# -------------------------- SYSTEM CLOCK ------------------------------------
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set_io --warn-no-port CLK 21
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# -------------------------- FTDI --------------------------------------------
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# --- FTDI 0:
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set_io --warn-no-port RES 66
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set_io --warn-no-port DONE 65
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set_io --warn-no-port SS 71
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set_io --warn-no-port MISO 67
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set_io --warn-no-port MOSI 68
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set_io --warn-no-port SCK 70
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#
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# --- FTDI 1: (Serial port)
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set_io --warn-no-port DCD 1
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set_io --warn-no-port DSR 2
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set_io --warn-no-port DTR 3
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set_io --warn-no-port CTS 4
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set_io --warn-no-port RTS 7
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set_io --warn-no-port TX 8
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set_io --warn-no-port RX 9
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