2018-12-28 22:51:28 +00:00
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###############################################################################
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#
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# TinyFPGA BX constraint file (.pcf)
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#
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###############################################################################
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#
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# Copyright (c) 2018, Luke Valenty
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of the <project name> project.
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#
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###############################################################################
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####
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# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
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####
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# Left side of board
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set_io --warn-no-port PIN_1 A2
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set_io --warn-no-port PIN_2 A1
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set_io --warn-no-port PIN_3 B1
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set_io --warn-no-port PIN_4 C2
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set_io --warn-no-port PIN_5 C1
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set_io --warn-no-port PIN_6 D2
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set_io --warn-no-port PIN_9 E1
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set_io --warn-no-port PIN_10 G2
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set_io --warn-no-port PIN_11 H1
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set_io --warn-no-port PIN_12 J1
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set_io --warn-no-port PIN_13 H2
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# Right side of board
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set_io --warn-no-port PIN_14 H9
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set_io --warn-no-port PIN_15 D9
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set_io --warn-no-port PIN_16 D8
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set_io --warn-no-port PIN_17 C9
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set_io --warn-no-port PIN_18 A9
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set_io --warn-no-port PIN_19 B8
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set_io --warn-no-port PIN_20 A8
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set_io --warn-no-port PIN_21 B7
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set_io --warn-no-port PIN_22 A7
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# LED
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set_io --warn-no-port LED B3
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# USB
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set_io --warn-no-port USBPU A3
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# 16MHz clock
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2018-12-29 19:08:26 +00:00
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# set_io --warn-no-port CLK B2 # input
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