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Update FPGA experiments. 

+ Separate out into per-board directories.
+ Add icestick hello world.
+ Add TinyFPGA hello world, beacon, button-triggered LED, and TinyAdder.
+ Add platform constraint files for the iCEStick and TinyFPGA.
This commit is contained in:
Kyle Isom 2018-12-28 20:45:02 -08:00
parent d47661659c
commit 2f086a2c28
24 changed files with 743 additions and 1 deletions
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91
fpga/adder.v Normal file
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@ -0,0 +1,91 @@
module half_adder (
input a,
input b,
output sum,
output carry
);
sum = a ^ b;
carry = a & b;
endmodule
module full_adder (
input a;
input b;
input carry_in;
output sum;
output carry_out;
);
wire carry_1;
wire carry_2;
// Intermediate output from first half-adder.
wire sum_1;
half_adder ha_low (
.a(a),
.b(b),
.carry(carry_1),
.sum(sum_1)
);
half_adder ha_high (
.a(sum_1),
.b(carry_1),
.carry(carry_2),
.sum(sum)
);
assign carry_out = carry_1 | carry_2;
endmodule
module addition_unit #(
ADDER_WIDTH = 4
) (
input carry_in;
input [ADDER_WIDTH-1:0] a,
input [ADDER_WIDTH-1:0] b,
output [ADDER_WIDTH-1:0] sum,
output carry_out
)
wire [ADDER_WIDTH-1:0] carry_chain;
genvar i;
generate
for (i = 0; i < ADDER_WIDTH; i = i + 1) begin
full_adder fa (
.a(a[i]),
.b(b[i]),
.sum(sum[i]),
.carry_in(carry_chain[i]),
.carry_out(carry_chain[i+1])
);
end
endgenerate
// Assign carry_in and carry_out to the beginning and end of the
// carry chain.
assign carry_chain[0] = carry_in;
assign carry_chain[ADDER_WIDTH] = carry_out;
endmodule
module better_addition_unit #(
ADDER_WIDTH = 8
) (
input carry_in;
input [ADDER_WIDTH-1:0] a,
input [ADDER_WIDTH-1:0] b,
output [ADDER_WIDTH-1:0] sum,
output carry_out
);
wire [ADDER_WIDTH:0] full_sum;
assign full_sum = carry_in + a + b;
assign carry_out = full_sum[ADDER_WIDTH];
endmodule

142
fpga/icestick.pcf Normal file
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# -----------------------------------------------------------------------------
#- Icestick constraint file (.pcf)
#- By Juan Gonzalez (Obijuan)
#- April - 2016
#- GPL license
# -----------------------------------------------------------------------------
# -- Pinout: http://www.pighixxx.com/test/2016/02/icestick-pinout/
# -- Guide: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/icestickusermanual.pdf
# -- Icestick leds map
#
# D1
# D4 D5 D2
# D3
#
# -- D1-D4: Red leds
# -- D5: green led
# ------------ Red leds ------------------------------------------------------
set_io --warn-no-port D1 99
set_io --warn-no-port D2 98
set_io --warn-no-port D3 97
set_io --warn-no-port D4 96
# ------------ Green led -----------------------------------------------------
set_io --warn-no-port D5 95
# ------------ IrDA ----------------------------------------------------------
set_io --warn-no-port IrDA_TX 105
set_io --warn-no-port IrDA_RX 106
#-- SD = 0, enable IrDA
set_io --warn-no-port SD 107
# ------------ PMOD connector ------------------------------------------------
#
# Pmod standar numeration (Oriented according the icestick, with the
# usb connector pointing to the left and IRda to the right)
#
# --------
# | 12 6 |
# | 11 5 |
# | 10 4 |
# | 9 3 |
# | 8 2 |
# | 7 1 | <
# --------
#
# FPGA pins:
#
# ----------
# | 3V3 3V3 |
# | GND GND |
# | 91 81 |
# | 90 80 |
# | 88 79 |
# | 87 78 | <
# ----------
#
set_io --warn-no-port PMOD1 78
set_io --warn-no-port PMOD2 79
set_io --warn-no-port PMOD3 80
set_io --warn-no-port PMOD4 81
set_io --warn-no-port PMOD7 87
set_io --warn-no-port PMOD8 88
set_io --warn-no-port PMOD9 90
set_io --warn-no-port PMOD10 91
# ------------------------ EXPANSION I/O ------------------------------------
#
# -- Numeration
#
# Top Row (TR):
# v
# --------------------------------
# | 10 9 8 7 6 5 4 3 2 1 |
# --------------------------------
#
# Bottom Row (BR):
#
# v
# --------------------------------
# | 10 9 8 7 6 5 4 3 2 1 |
# --------------------------------
#
# --- FPGA pins
#
# Top Row (TR)
# v
# --------------------------------------------------
# | 119 118 117 116 115 114 113 112 GND 3v3 |
# --------------------------------------------------
#
#
# Bottom Row (BR)
#
# v
# -------------------------------------------------
# | 44 45 47 48 56 60 61 62 GND 3v3 |
# -------------------------------------------------
#
# -- Top Row
set_io --warn-no-port TR3 112
set_io --warn-no-port TR4 113
set_io --warn-no-port TR5 114
set_io --warn-no-port TR6 115
set_io --warn-no-port TR7 116
set_io --warn-no-port TR8 117
set_io --warn-no-port TR9 118
set_io --warn-no-port TR10 119
#
# -- Bottom Row
set_io --warn-no-port BR3 62
set_io --warn-no-port BR4 61
set_io --warn-no-port BR5 60
set_io --warn-no-port BR6 56
set_io --warn-no-port BR7 48
set_io --warn-no-port BR8 47
set_io --warn-no-port BR9 45
set_io --warn-no-port BR10 44
# -------------------------- SYSTEM CLOCK ------------------------------------
set_io --warn-no-port CLK 21
# -------------------------- FTDI --------------------------------------------
# --- FTDI 0:
set_io --warn-no-port RES 66
set_io --warn-no-port DONE 65
set_io --warn-no-port SS 71
set_io --warn-no-port MISO 67
set_io --warn-no-port MOSI 68
set_io --warn-no-port SCK 70
#
# --- FTDI 1: (Serial port)
set_io --warn-no-port DCD 1
set_io --warn-no-port DSR 2
set_io --warn-no-port DTR 3
set_io --warn-no-port CTS 4
set_io --warn-no-port RTS 7
set_io --warn-no-port TX 8
set_io --warn-no-port RX 9

3
fpga/icestick/hello/apio.ini Normal file
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@ -0,0 +1,3 @@
[env]
board = icestick

142
fpga/icestick/hello/pins.pcf Normal file
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# -----------------------------------------------------------------------------
#- Icestick constraint file (.pcf)
#- By Juan Gonzalez (Obijuan)
#- April - 2016
#- GPL license
# -----------------------------------------------------------------------------
# -- Pinout: http://www.pighixxx.com/test/2016/02/icestick-pinout/
# -- Guide: https://github.com/Obijuan/open-fpga-verilog-tutorial/blob/master/tutorial/doc/icestickusermanual.pdf
# -- Icestick leds map
#
# D1
# D4 D5 D2
# D3
#
# -- D1-D4: Red leds
# -- D5: green led
# ------------ Red leds ------------------------------------------------------
set_io --warn-no-port D1 99
set_io --warn-no-port D2 98
set_io --warn-no-port D3 97
set_io --warn-no-port D4 96
# ------------ Green led -----------------------------------------------------
set_io --warn-no-port D5 95
# ------------ IrDA ----------------------------------------------------------
set_io --warn-no-port IrDA_TX 105
set_io --warn-no-port IrDA_RX 106
#-- SD = 0, enable IrDA
set_io --warn-no-port SD 107
# ------------ PMOD connector ------------------------------------------------
#
# Pmod standar numeration (Oriented according the icestick, with the
# usb connector pointing to the left and IRda to the right)
#
# --------
# | 12 6 |
# | 11 5 |
# | 10 4 |
# | 9 3 |
# | 8 2 |
# | 7 1 | <
# --------
#
# FPGA pins:
#
# ----------
# | 3V3 3V3 |
# | GND GND |
# | 91 81 |
# | 90 80 |
# | 88 79 |
# | 87 78 | <
# ----------
#
set_io --warn-no-port PMOD1 78
set_io --warn-no-port PMOD2 79
set_io --warn-no-port PMOD3 80
set_io --warn-no-port PMOD4 81
set_io --warn-no-port PMOD7 87
set_io --warn-no-port PMOD8 88
set_io --warn-no-port PMOD9 90
set_io --warn-no-port PMOD10 91
# ------------------------ EXPANSION I/O ------------------------------------
#
# -- Numeration
#
# Top Row (TR):
# v
# --------------------------------
# | 10 9 8 7 6 5 4 3 2 1 |
# --------------------------------
#
# Bottom Row (BR):
#
# v
# --------------------------------
# | 10 9 8 7 6 5 4 3 2 1 |
# --------------------------------
#
# --- FPGA pins
#
# Top Row (TR)
# v
# --------------------------------------------------
# | 119 118 117 116 115 114 113 112 GND 3v3 |
# --------------------------------------------------
#
#
# Bottom Row (BR)
#
# v
# -------------------------------------------------
# | 44 45 47 48 56 60 61 62 GND 3v3 |
# -------------------------------------------------
#
# -- Top Row
set_io --warn-no-port TR3 112
set_io --warn-no-port TR4 113
set_io --warn-no-port TR5 114
set_io --warn-no-port TR6 115
set_io --warn-no-port TR7 116
set_io --warn-no-port TR8 117
set_io --warn-no-port TR9 118
set_io --warn-no-port TR10 119
#
# -- Bottom Row
set_io --warn-no-port BR3 62
set_io --warn-no-port BR4 61
set_io --warn-no-port BR5 60
set_io --warn-no-port BR6 56
set_io --warn-no-port BR7 48
set_io --warn-no-port BR8 47
set_io --warn-no-port BR9 45
set_io --warn-no-port BR10 44
# -------------------------- SYSTEM CLOCK ------------------------------------
set_io --warn-no-port CLK 21
# -------------------------- FTDI --------------------------------------------
# --- FTDI 0:
set_io --warn-no-port RES 66
set_io --warn-no-port DONE 65
set_io --warn-no-port SS 71
set_io --warn-no-port MISO 67
set_io --warn-no-port MOSI 68
set_io --warn-no-port SCK 70
#
# --- FTDI 1: (Serial port)
set_io --warn-no-port DCD 1
set_io --warn-no-port DSR 2
set_io --warn-no-port DTR 3
set_io --warn-no-port CTS 4
set_io --warn-no-port RTS 7
set_io --warn-no-port TX 8
set_io --warn-no-port RX 9

28
fpga/icestick/hello/top.v Normal file
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@ -0,0 +1,28 @@
module top (
input CLK,
output D1,
output D2,
output D3,
output D4,
output D5
);
reg [20:0] clock_counter;
reg [3:0] active = 0;
reg [9:0] pattern = 10'b1010000000;
wire [4:0] leds;
assign leds = {D5, D4, D3, D2, D1};
always @(posedge CLK) begin
clock_counter <= clock_counter + 1;
if (clock_counter == 21'b100100100111110000000) begin
if (pattern[active] == 1)
leds = 5'b11111;
else
leds = 5'b00000;
active <= active + 1;
if (active == 4'b1011) active <= 0;
end
end
endmodule

0
fpga/adder/pins.pcf → fpga/tinyfpga.pcf
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2
fpga/adder/top.v → fpga/tinyfpga/TinyAdder/TinyAdder.v
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@ -28,7 +28,7 @@ module segment7 (
endmodule
// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
module TinyAdder (
input CLK, // 16MHz clock
input PIN_1, // A[0]
input PIN_2, // A[1]

0
fpga/adder/apio.ini → fpga/tinyfpga/TinyAdder/apio.ini
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0
fpga/adder/install_apio.sh → fpga/tinyfpga/TinyAdder/install_apio.sh
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0
fpga/beacon/pins.pcf → fpga/tinyfpga/TinyAdder/pins.pcf
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0
fpga/adder/adder_fpga.brd → fpga/tinyfpga/TinyAdder/tinyadder_r2.brd
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0
fpga/adder/adder_fpga.sch → fpga/tinyfpga/TinyAdder/tinyadder_r2.sch
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0
fpga/beacon/apio.ini → fpga/tinyfpga/beacon/apio.ini
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0
fpga/beacon/install_apio.sh → fpga/tinyfpga/beacon/install_apio.sh
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94
fpga/tinyfpga/beacon/pins.pcf Normal file
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@ -0,0 +1,94 @@
###############################################################################
#
# TinyFPGA BX constraint file (.pcf)
#
###############################################################################
#
# Copyright (c) 2018, Luke Valenty
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of the <project name> project.
#
###############################################################################
####
# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
####
# Left side of board
set_io --warn-no-port PIN_1 A2
set_io --warn-no-port PIN_2 A1
set_io --warn-no-port PIN_3 B1
set_io --warn-no-port PIN_4 C2
set_io --warn-no-port PIN_5 C1
set_io --warn-no-port PIN_6 D2
set_io --warn-no-port PIN_7 D1
set_io --warn-no-port PIN_8 E2
set_io --warn-no-port PIN_9 E1
set_io --warn-no-port PIN_10 G2
set_io --warn-no-port PIN_11 H1
set_io --warn-no-port PIN_12 J1
set_io --warn-no-port PIN_13 H2
# Right side of board
set_io --warn-no-port PIN_14 H9
set_io --warn-no-port PIN_15 D9
set_io --warn-no-port PIN_16 D8
set_io --warn-no-port PIN_17 C9
set_io --warn-no-port PIN_18 A9
set_io --warn-no-port PIN_19 B8
set_io --warn-no-port PIN_20 A8
set_io --warn-no-port PIN_21 B7
set_io --warn-no-port PIN_22 A7
set_io --warn-no-port PIN_23 B6
set_io --warn-no-port PIN_24 A6
# SPI flash interface on bottom of board
set_io --warn-no-port SPI_SS F7
set_io --warn-no-port SPI_SCK G7
set_io --warn-no-port SPI_IO0 G6
set_io --warn-no-port SPI_IO1 H7
set_io --warn-no-port SPI_IO2 H4
set_io --warn-no-port SPI_IO3 J8
# General purpose pins on bottom of board
set_io --warn-no-port PIN_25 G1
set_io --warn-no-port PIN_26 J3
set_io --warn-no-port PIN_27 J4
set_io --warn-no-port PIN_28 G9
set_io --warn-no-port PIN_29 J9
set_io --warn-no-port PIN_30 E8
set_io --warn-no-port PIN_31 J2
# LED
set_io --warn-no-port LED B3
# USB
set_io --warn-no-port USBP B4
set_io --warn-no-port USBN A4
set_io --warn-no-port USBPU A3
# 16MHz clock
set_io --warn-no-port CLK B2 # input

0
fpga/beacon/top.v → fpga/tinyfpga/beacon/top.v
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1
fpga/tinyfpga/bled/apio.ini Normal file
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@ -0,0 +1 @@
{"board": "TinyFPGA-BX"}

94
fpga/tinyfpga/bled/pins.pcf Normal file
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@ -0,0 +1,94 @@
###############################################################################
#
# TinyFPGA BX constraint file (.pcf)
#
###############################################################################
#
# Copyright (c) 2018, Luke Valenty
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of the <project name> project.
#
###############################################################################
####
# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
####
# Left side of board
set_io --warn-no-port PIN_1 A2
set_io --warn-no-port PIN_2 A1
set_io --warn-no-port PIN_3 B1
set_io --warn-no-port PIN_4 C2
set_io --warn-no-port PIN_5 C1
set_io --warn-no-port PIN_6 D2
set_io --warn-no-port PIN_7 D1
set_io --warn-no-port PIN_8 E2
set_io --warn-no-port PIN_9 E1
set_io --warn-no-port PIN_10 G2
set_io --warn-no-port PIN_11 H1
set_io --warn-no-port PIN_12 J1
set_io --warn-no-port PIN_13 H2
# Right side of board
set_io --warn-no-port PIN_14 H9
set_io --warn-no-port PIN_15 D9
set_io --warn-no-port PIN_16 D8
set_io --warn-no-port PIN_17 C9
set_io --warn-no-port PIN_18 A9
set_io --warn-no-port PIN_19 B8
set_io --warn-no-port PIN_20 A8
set_io --warn-no-port PIN_21 B7
set_io --warn-no-port PIN_22 A7
set_io --warn-no-port PIN_23 B6
set_io --warn-no-port PIN_24 A6
# SPI flash interface on bottom of board
set_io --warn-no-port SPI_SS F7
set_io --warn-no-port SPI_SCK G7
set_io --warn-no-port SPI_IO0 G6
set_io --warn-no-port SPI_IO1 H7
set_io --warn-no-port SPI_IO2 H4
set_io --warn-no-port SPI_IO3 J8
# General purpose pins on bottom of board
set_io --warn-no-port PIN_25 G1
set_io --warn-no-port PIN_26 J3
set_io --warn-no-port PIN_27 J4
set_io --warn-no-port PIN_28 G9
set_io --warn-no-port PIN_29 J9
set_io --warn-no-port PIN_30 E8
set_io --warn-no-port PIN_31 J2
# LED
set_io --warn-no-port LED B3
# USB
set_io --warn-no-port USBP B4
set_io --warn-no-port USBN A4
set_io --warn-no-port USBPU A3
# 16MHz clock
set_io --warn-no-port CLK B2 # input

14
fpga/tinyfpga/bled/top.v Normal file
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@ -0,0 +1,14 @@
/// bled
/// Button-press LED
///
/// This connects a pushbutton on pin 6 to the LED. The pushbutton has one
/// side connected to Vcc, and the other side to both pin 6 and a 10K
/// Ω resistor (because, for some reason, that's what I have on hand).
module top (
input PIN_6,
output LED
);
assign LED = PIN_6;
endmodule

3
fpga/tinyfpga/hello_world/apio.ini Normal file
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@ -0,0 +1,3 @@
[env]
board = TinyFPGA-BX

5
fpga/tinyfpga/hello_world/install_apio.bat Normal file
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@ -0,0 +1,5 @@
pip install apio==0.4.0b3 tinyprog
apio install system scons icestorm drivers
apio drivers --serial-enable
@pause

4
fpga/tinyfpga/hello_world/install_apio.sh Normal file
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@ -0,0 +1,4 @@
pip install apio==0.4.0b3 tinyprog
apio install system scons icestorm drivers
apio drivers --serial-enable

94
fpga/tinyfpga/hello_world/pins.pcf Normal file
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@ -0,0 +1,94 @@
###############################################################################
#
# TinyFPGA BX constraint file (.pcf)
#
###############################################################################
#
# Copyright (c) 2018, Luke Valenty
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of the <project name> project.
#
###############################################################################
####
# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
####
# Left side of board
set_io --warn-no-port PIN_1 A2
set_io --warn-no-port PIN_2 A1
set_io --warn-no-port PIN_3 B1
set_io --warn-no-port PIN_4 C2
set_io --warn-no-port PIN_5 C1
set_io --warn-no-port PIN_6 D2
set_io --warn-no-port PIN_7 D1
set_io --warn-no-port PIN_8 E2
set_io --warn-no-port PIN_9 E1
set_io --warn-no-port PIN_10 G2
set_io --warn-no-port PIN_11 H1
set_io --warn-no-port PIN_12 J1
set_io --warn-no-port PIN_13 H2
# Right side of board
set_io --warn-no-port PIN_14 H9
set_io --warn-no-port PIN_15 D9
set_io --warn-no-port PIN_16 D8
set_io --warn-no-port PIN_17 C9
set_io --warn-no-port PIN_18 A9
set_io --warn-no-port PIN_19 B8
set_io --warn-no-port PIN_20 A8
set_io --warn-no-port PIN_21 B7
set_io --warn-no-port PIN_22 A7
set_io --warn-no-port PIN_23 B6
set_io --warn-no-port PIN_24 A6
# SPI flash interface on bottom of board
set_io --warn-no-port SPI_SS F7
set_io --warn-no-port SPI_SCK G7
set_io --warn-no-port SPI_IO0 G6
set_io --warn-no-port SPI_IO1 H7
set_io --warn-no-port SPI_IO2 H4
set_io --warn-no-port SPI_IO3 J8
# General purpose pins on bottom of board
set_io --warn-no-port PIN_25 G1
set_io --warn-no-port PIN_26 J3
set_io --warn-no-port PIN_27 J4
set_io --warn-no-port PIN_28 G9
set_io --warn-no-port PIN_29 J9
set_io --warn-no-port PIN_30 E8
set_io --warn-no-port PIN_31 J2
# LED
set_io --warn-no-port LED B3
# USB
set_io --warn-no-port USBP B4
set_io --warn-no-port USBN A4
set_io --warn-no-port USBPU A3
# 16MHz clock
set_io --warn-no-port CLK B2 # input

27
fpga/tinyfpga/hello_world/top.v Normal file
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// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
////////
// make a simple blink circuit
////////
// keep track of time and location in blink_pattern
reg [25:0] blink_counter;
// pattern that will be flashed over the LED over time
wire [31:0] blink_pattern = 32'b101010001110111011100010101;
// increment the blink_counter every clock
always @(posedge CLK) begin
blink_counter <= blink_counter + 1;
end
// light up the LED according to the pattern
assign LED = blink_pattern[blink_counter[25:21]];
endmodule