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fpga: add TinyAdder rev1

This commit is contained in:
Kyle Isom 2018-12-28 14:51:28 -08:00
parent 729a5b3037
commit 8080d93084
4 changed files with 203 additions and 0 deletions
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3
fpga/adder/apio.ini Normal file
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[env]
board = TinyFPGA-BX

4
fpga/adder/install_apio.sh Normal file
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pip install apio==0.4.0b3 tinyprog
apio install system scons icestorm drivers
apio drivers --serial-enable

94
fpga/adder/pins.pcf Normal file
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###############################################################################
#
# TinyFPGA BX constraint file (.pcf)
#
###############################################################################
#
# Copyright (c) 2018, Luke Valenty
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of the <project name> project.
#
###############################################################################
####
# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
####
# Left side of board
set_io --warn-no-port PIN_1 A2
set_io --warn-no-port PIN_2 A1
set_io --warn-no-port PIN_3 B1
set_io --warn-no-port PIN_4 C2
set_io --warn-no-port PIN_5 C1
set_io --warn-no-port PIN_6 D2
set_io --warn-no-port PIN_7 D1
set_io --warn-no-port PIN_8 E2
set_io --warn-no-port PIN_9 E1
set_io --warn-no-port PIN_10 G2
set_io --warn-no-port PIN_11 H1
set_io --warn-no-port PIN_12 J1
set_io --warn-no-port PIN_13 H2
# Right side of board
set_io --warn-no-port PIN_14 H9
set_io --warn-no-port PIN_15 D9
set_io --warn-no-port PIN_16 D8
set_io --warn-no-port PIN_17 C9
set_io --warn-no-port PIN_18 A9
set_io --warn-no-port PIN_19 B8
set_io --warn-no-port PIN_20 A8
set_io --warn-no-port PIN_21 B7
set_io --warn-no-port PIN_22 A7
set_io --warn-no-port PIN_23 B6
set_io --warn-no-port PIN_24 A6
# SPI flash interface on bottom of board
set_io --warn-no-port SPI_SS F7
set_io --warn-no-port SPI_SCK G7
set_io --warn-no-port SPI_IO0 G6
set_io --warn-no-port SPI_IO1 H7
set_io --warn-no-port SPI_IO2 H4
set_io --warn-no-port SPI_IO3 J8
# General purpose pins on bottom of board
set_io --warn-no-port PIN_25 G1
set_io --warn-no-port PIN_26 J3
set_io --warn-no-port PIN_27 J4
set_io --warn-no-port PIN_28 G9
set_io --warn-no-port PIN_29 J9
set_io --warn-no-port PIN_30 E8
set_io --warn-no-port PIN_31 J2
# LED
set_io --warn-no-port LED B3
# USB
set_io --warn-no-port USBP B4
set_io --warn-no-port USBN A4
set_io --warn-no-port USBPU A3
# 16MHz clock
set_io --warn-no-port CLK B2 # input

102
fpga/adder/top.v Normal file
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module segment7 (
input [3:0] number,
output [6:0] out = 7'b0000000
);
always @(*)
begin
case (number)
4'b0000: out <= 7'b0111111; // 0
4'b0001: out <= 7'b0000110; // 1
4'b0010: out <= 7'b1011011; // 2
4'b0011: out <= 7'b1001111; // 3
4'b0100: out <= 7'b1100110; // 4
4'b0101: out <= 7'b1101101; // 5
4'b0110: out <= 7'b1111101; // 6
4'b0111: out <= 7'b0000111; // 7
4'b1000: out <= 7'b1111111; // 8
4'b1001: out <= 7'b1100111; // 9
4'b1010: out <= 7'b1110111; // A
4'b1011: out <= 7'b1111100; // B
4'b1100: out <= 7'b0111001; // C
4'b1101: out <= 7'b1011110; // D
4'b1110: out <= 7'b1111001; // E
4'b1111: out <= 7'b1110001; // F
endcase
end
endmodule
// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
input CLK, // 16MHz clock
input PIN_1, // A[0]
input PIN_2, // A[1]
input PIN_3, // A[2]
input PIN_4, // A[3]
input PIN_5, // EXEC
input PIN_6, // CLR
// 7-segment LCD displays
output PIN_9, // LOW/A
output PIN_10, // LOW/B
output PIN_11, // LOW/C
output PIN_12, // LOW/D
output PIN_13, // LOW/E
output PIN_14, // LOW/F
output PIN_15, // LOW/G
output PIN_16, // HI/A
output PIN_17, // HI/B
output PIN_18, // HI/C
output PIN_19, // HI/D
output PIN_20, // HI/E
output PIN_21, // HI/F
output PIN_22, // HI/G
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
wire [7:0] sum = 8'b00000000;
wire [3:0] switches;
assign switches = {PIN_4, PIN_3, PIN_2, PIN_1};
// state determines what happens when the button is pressed.
reg [1:0] state = 2'b00;
assign LED = state[0];
segment7 low (
.number(sum[3:0]),
.out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9})
);
segment7 hi (
.number(sum[7:4]),
.out({PIN_22, PIN_21, PIN_20, PIN_19, PIN_18, PIN_17, PIN_16})
);
always @(PIN_5)
begin
case (state)
2'b00: begin
sum = switches;
state <= 2'b01;
end
2'b01: begin
sum = sum + switches;
state = 2'b10;
end
endcase
end
always @(PIN_6)
begin
state <= 2'b00;
sum = 7'b0000000;
end
endmodule