fpga: 7-segment test on TinyFPGA.

fpga/tinyfpga/SegmentLCD/SegmentLCD.v

@@ -0,0 +1,41 @@
+/// SegmentLCD represents a 7-segment display that takes as input a 4-bit
+/// number and outputs the correct pin configuration. The pins need to be
+/// wired as {G, F, E, D, C, B, A} for this to work.
+///
+/// For example,
+/// 
+///	wire [7:0]	sum = 8'b00000000;
+///	segment7 low (
+///		.number(sum[3:0]),
+///		.out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9})
+///	);
+module SegmentLCD (
+	input	[3:0]		number,
+	output	reg [6:0]	out
+);
+
+	always @(*)
+	begin
+		case (number)
+			4'b0000: out = ~7'b0111111; // 0
+			4'b0001: out = ~7'b0000110; // 1
+			4'b0010: out = ~7'b1011011; // 2
+			4'b0011: out = ~7'b1001111; // 3
+			4'b0100: out = ~7'b1100110; // 4
+			4'b0101: out = ~7'b1101101; // 5
+			4'b0110: out = ~7'b1111101; // 6
+			4'b0111: out = ~7'b0000111; // 7
+			4'b1000: out = ~7'b1111111; // 8
+			4'b1001: out = ~7'b1100111; // 9
+			4'b1010: out = ~7'b1110111; // A
+			4'b1011: out = ~7'b1111100; // B
+			4'b1100: out = ~7'b0111001; // C
+			4'b1101: out = ~7'b1011110; // D
+			4'b1110: out = ~7'b1111001; // E
+			4'b1111: out = ~7'b1110001; // F	
+		endcase
+	end
+
+endmodule
+
+

fpga/tinyfpga/SegmentLCD/apio.ini

@@ -0,0 +1,3 @@
+[env]
+board = TinyFPGA-BX
+

fpga/tinyfpga/SegmentLCD/pins.pcf

@@ -0,0 +1,49 @@
+###############################################################################
+#
+# TinyFPGA BX constraint file (.pcf)
+#
+###############################################################################
+#
+# Copyright (c) 2018, Luke Valenty
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# 
+# 1. Redistributions of source code must retain the above copyright notice, this
+#    list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+#    this list of conditions and the following disclaimer in the documentation
+#    and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of the <project name> project. 
+#
+###############################################################################
+
+####
+# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
+####
+
+# Left side of board
+set_io --warn-no-port PIN_9 E1
+set_io --warn-no-port PIN_10 G2
+set_io --warn-no-port PIN_11 H1
+set_io --warn-no-port PIN_12 J1
+set_io --warn-no-port PIN_13 H2
+set_io --warn-no-port PIN_14 H9
+set_io --warn-no-port PIN_15 D9
+set_io --warn-no-port USBPU A3
+set_io --warn-no-port CLK B2 # input

fpga/tinyfpga/SegmentLCD/top.v

@@ -0,0 +1,30 @@
+module SegmentLCDTest (
+	input	CLK,
+	output	PIN_9,
+	output	PIN_10,
+	output	PIN_11,
+	output	PIN_12,
+	output	PIN_13,
+	output	PIN_14,
+	output	PIN_15,
+	output	USBPU
+);
+
+	assign USBPU = 0;
+
+	reg [21:0]	clock_counter = 21'b0000000000000000000000;
+	reg [3:0]	number = 4'b0000;
+
+	SegmentLCD	display (
+		.number(number),
+		.out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9})
+	);
+
+	always @(posedge CLK) begin
+		clock_counter <= clock_counter + 1;
+		if (clock_counter == 22'b1100001101010000000000) begin
+			number <= number + 1;
+			clock_counter <= 0;
+		end
+	end
+endmodule

fpga/tinyfpga/TinyAdder/SegmentLCD.v

@@ -11,28 +11,28 @@
 ///	);
 module SegmentLCD (
 	input	[3:0]		number,
-	output	[6:0]	out = 7'b0000000
+	output	reg [6:0]	out
 );
 
 	always @(*)
 	begin
 		case (number)
-			4'b0000: out <= 7'b0111111; // 0
+			4'b0000: out = ~7'b0111111; // 0
-			4'b0001: out <= 7'b0000110; // 1
+			4'b0001: out = ~7'b0000110; // 1
-			4'b0010: out <= 7'b1011011; // 2
+			4'b0010: out = ~7'b1011011; // 2
-			4'b0011: out <= 7'b1001111; // 3
+			4'b0011: out = ~7'b1001111; // 3
-			4'b0100: out <= 7'b1100110; // 4
+			4'b0100: out = ~7'b1100110; // 4
-			4'b0101: out <= 7'b1101101; // 5
+			4'b0101: out = ~7'b1101101; // 5
-			4'b0110: out <= 7'b1111101; // 6
+			4'b0110: out = ~7'b1111101; // 6
-			4'b0111: out <= 7'b0000111; // 7
+			4'b0111: out = ~7'b0000111; // 7
-			4'b1000: out <= 7'b1111111; // 8
+			4'b1000: out = ~7'b1111111; // 8
-			4'b1001: out <= 7'b1100111; // 9
+			4'b1001: out = ~7'b1100111; // 9
-			4'b1010: out <= 7'b1110111; // A
+			4'b1010: out = ~7'b1110111; // A
-			4'b1011: out <= 7'b1111100; // B
+			4'b1011: out = ~7'b1111100; // B
-			4'b1100: out <= 7'b0111001; // C
+			4'b1100: out = ~7'b0111001; // C
-			4'b1101: out <= 7'b1011110; // D
+			4'b1101: out = ~7'b1011110; // D
-			4'b1110: out <= 7'b1111001; // E
+			4'b1110: out = ~7'b1111001; // E
-			4'b1111: out <= 7'b1110001; // F	
+			4'b1111: out = ~7'b1110001; // F	
 		endcase
 	end