33 lines
562 B
Verilog
33 lines
562 B
Verilog
module SegmentLCDTest (
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input CLK,
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output D1,
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output D2,
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output D3,
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output D4,
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output D5,
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output BR4,
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output BR5,
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output BR6,
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output BR7,
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output BR8,
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output BR9,
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output BR10
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);
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reg [21:0] clock_counter = 22'b00000000000000000000000;
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reg [3:0] number = 4'b0000;
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SegmentLCD display (
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.number(number),
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.out({BR10, BR9, BR8, BR7, BR6, BR5, BR4})
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);
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always @(posedge CLK) begin
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clock_counter <= clock_counter + 1;
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if (clock_counter == 22'b1001001001111100000000) begin
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number <= number + 1;
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clock_counter <= 0;
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end
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end
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endmodule
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