29 lines
520 B
Verilog
29 lines
520 B
Verilog
module top (
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input CLK,
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output D1,
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output D2,
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output D3,
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output D4,
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output D5
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);
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reg [20:0] clock_counter;
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reg [3:0] active = 0;
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reg [9:0] pattern = 10'b1010000000;
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wire [4:0] leds;
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assign leds = {D5, D4, D3, D2, D1};
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always @(posedge CLK) begin
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clock_counter <= clock_counter + 1;
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if (clock_counter == 21'b100100100111110000000) begin
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if (pattern[active] == 1)
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leds = 5'b11111;
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else
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leds = 5'b00000;
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active <= active + 1;
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if (active == 4'b1011) active <= 0;
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end
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end
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endmodule
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