42 lines
1.1 KiB
Verilog
42 lines
1.1 KiB
Verilog
/// SegmentLCD represents a 7-segment display that takes as input a 4-bit
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/// number and outputs the correct pin configuration. The pins need to be
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/// wired as {G, F, E, D, C, B, A} for this to work.
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///
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/// For example,
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///
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/// wire [7:0] sum = 8'b00000000;
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/// segment7 low (
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/// .number(sum[3:0]),
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/// .out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9})
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/// );
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module SegmentLCD (
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input [3:0] number,
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output reg [6:0] out
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);
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always @(*)
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begin
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case (number)
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4'b0000: out = ~7'b0111111; // 0
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4'b0001: out = ~7'b0000110; // 1
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4'b0010: out = ~7'b1011011; // 2
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4'b0011: out = ~7'b1001111; // 3
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4'b0100: out = ~7'b1100110; // 4
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4'b0101: out = ~7'b1101101; // 5
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4'b0110: out = ~7'b1111101; // 6
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4'b0111: out = ~7'b0000111; // 7
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4'b1000: out = ~7'b1111111; // 8
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4'b1001: out = ~7'b1100111; // 9
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4'b1010: out = ~7'b1110111; // A
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4'b1011: out = ~7'b1111100; // B
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4'b1100: out = ~7'b0111001; // C
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4'b1101: out = ~7'b1011110; // D
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4'b1110: out = ~7'b1111001; // E
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4'b1111: out = ~7'b1110001; // F
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endcase
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end
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endmodule
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