31 lines
574 B
Verilog
31 lines
574 B
Verilog
module SegmentLCDTest (
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input CLK,
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output PIN_9,
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output PIN_10,
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output PIN_11,
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output PIN_12,
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output PIN_13,
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output PIN_14,
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output PIN_15,
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output USBPU
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);
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assign USBPU = 0;
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reg [21:0] clock_counter = 21'b0000000000000000000000;
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reg [3:0] number = 4'b0000;
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SegmentLCD display (
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.number(number),
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.out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9})
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);
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always @(posedge CLK) begin
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clock_counter <= clock_counter + 1;
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if (clock_counter == 22'b1100001101010000000000) begin
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number <= number + 1;
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clock_counter <= 0;
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end
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end
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endmodule
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