103 lines
2.2 KiB
Verilog
103 lines
2.2 KiB
Verilog
module segment7 (
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input [3:0] number,
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output [6:0] out = 7'b0000000
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);
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always @(*)
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begin
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case (number)
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4'b0000: out <= 7'b0111111; // 0
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4'b0001: out <= 7'b0000110; // 1
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4'b0010: out <= 7'b1011011; // 2
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4'b0011: out <= 7'b1001111; // 3
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4'b0100: out <= 7'b1100110; // 4
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4'b0101: out <= 7'b1101101; // 5
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4'b0110: out <= 7'b1111101; // 6
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4'b0111: out <= 7'b0000111; // 7
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4'b1000: out <= 7'b1111111; // 8
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4'b1001: out <= 7'b1100111; // 9
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4'b1010: out <= 7'b1110111; // A
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4'b1011: out <= 7'b1111100; // B
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4'b1100: out <= 7'b0111001; // C
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4'b1101: out <= 7'b1011110; // D
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4'b1110: out <= 7'b1111001; // E
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4'b1111: out <= 7'b1110001; // F
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endcase
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end
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endmodule
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// look in pins.pcf for all the pin names on the TinyFPGA BX board
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module top (
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input CLK, // 16MHz clock
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input PIN_1, // A[0]
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input PIN_2, // A[1]
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input PIN_3, // A[2]
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input PIN_4, // A[3]
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input PIN_5, // EXEC
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input PIN_6, // CLR
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// 7-segment LCD displays
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output PIN_9, // LOW/A
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output PIN_10, // LOW/B
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output PIN_11, // LOW/C
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output PIN_12, // LOW/D
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output PIN_13, // LOW/E
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output PIN_14, // LOW/F
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output PIN_15, // LOW/G
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output PIN_16, // HI/A
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output PIN_17, // HI/B
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output PIN_18, // HI/C
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output PIN_19, // HI/D
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output PIN_20, // HI/E
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output PIN_21, // HI/F
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output PIN_22, // HI/G
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output LED, // User/boot LED next to power LED
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output USBPU // USB pull-up resistor
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);
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// drive USB pull-up resistor to '0' to disable USB
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assign USBPU = 0;
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wire [7:0] sum = 8'b00000000;
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wire [3:0] switches;
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assign switches = {PIN_4, PIN_3, PIN_2, PIN_1};
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// state determines what happens when the button is pressed.
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reg [1:0] state = 2'b00;
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assign LED = state[0];
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segment7 low (
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.number(sum[3:0]),
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.out({PIN_15, PIN_14, PIN_13, PIN_12, PIN_11, PIN_10, PIN_9})
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);
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segment7 hi (
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.number(sum[7:4]),
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.out({PIN_22, PIN_21, PIN_20, PIN_19, PIN_18, PIN_17, PIN_16})
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);
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always @(PIN_5)
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begin
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case (state)
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2'b00: begin
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sum = switches;
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state <= 2'b01;
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end
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2'b01: begin
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sum = sum + switches;
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state = 2'b10;
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end
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endcase
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end
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always @(PIN_6)
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begin
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state <= 2'b00;
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sum = 7'b0000000;
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end
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endmodule
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