25 lines
350 B
Verilog
25 lines
350 B
Verilog
/// btled: button-toggled LED.
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/// This is a port of the TinyFPGA btled to the iCEStick.
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module top (
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input BR10,
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output D1,
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output D2,
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output D3,
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output D4,
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output D5
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);
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reg state = 0;
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assign D1 = state;
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assign D2 = state;
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assign D3 = state;
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assign D4 = state;
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assign D5 = state;
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always @(negedge BR10) state <= !state;
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endmodule
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