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172 Commits

Author SHA1 Message Date
Kyle Isom 6b5d758311 Commit chapter 12 stuff from last night. 2019-04-29 12:36:13 -07:00
Kyle Isom d88b7f8bcf Finishing up part 1. 2019-04-25 23:02:54 -07:00
Kyle Isom 2796f1b209 Add a note. 2019-04-25 19:57:56 -07:00
Kyle Isom 26dcb6035a Finish chapter 7 code. 2019-04-25 19:18:39 -07:00
Kyle Isom dbbdcadb51 Fix permissions. 
Somehow this ended up 0777. It's now 664.
 2019-04-26 01:26:34 +00:00
Kyle Isom 270c94d536 Working on chapter 7 exercises. 2019-04-25 10:36:15 -07:00
Kyle Isom 8599658f0b Fix inverted logic case in file uploads. 2019-04-25 00:39:51 -07:00
Kyle Isom 92f9474f88 slow hacks 2019-04-25 01:39:19 +00:00
Kyle Isom 695b45d9c0 bus experiments 2019-04-24 22:46:05 +00:00
Kyle Isom 25979492cc pe: add compiled funs. 2019-04-24 18:49:14 +00:00
Kyle Isom 7b34ef9819 Add RGB. 2019-04-23 18:28:52 -07:00
Kyle Isom ebb8172551 From scratch forth text editor. 2019-04-23 18:28:32 -07:00
Kyle Isom 1d483e23ca add term stashing 
rip joe :(
 2019-04-22 23:17:19 -07:00
Kyle Isom 46c5fafa4f more erlang 
rip joe :(
 2019-04-22 23:16:59 -07:00
Kyle Isom e05f92d764 PE: Starting ch4 exercises. 2019-04-22 16:52:35 -07:00
Kyle Isom 6220e18137 Working through PE. 2019-04-22 23:49:46 +00:00
Kyle Isom 8450ce8753 Updating PE. 2019-04-22 07:01:00 -07:00
Kyle Isom ba841f127c Start programming erlang. 2019-04-21 19:25:01 -07:00
Kyle Isom bb0620f3aa Add perlin noise implementation. 2019-02-16 16:50:56 -08:00
Kyle Isom 0f5a237b10 Add NumberDisplay and SwitchLED. 2019-01-03 13:40:54 -08:00
Kyle Isom 5b7110fd24 bluepill: add usbcdc example 2019-01-02 19:58:24 -08:00
Kyle Isom 3d193b0275 fpga: add icestick segment LCD demo. 2019-01-02 16:29:31 -08:00
Kyle Isom b70f066f25 fpga: 7-segment test on TinyFPGA. 2019-01-02 14:58:17 -08:00
Kyle Isom 87f936d7b5 pio: add bluepill blink. 2018-12-31 09:00:46 -08:00
Kyle Isom ef5e3dc7fd fpga: add iCEStick btled example. 2018-12-29 14:03:45 -08:00
Kyle Isom 50b0827983 pio: nrf52 test blinks LED. 2018-12-29 14:02:49 -08:00
Kyle Isom fddd50e701 Remove unused register. 2018-12-29 14:02:29 -08:00
Kyle Isom 129f92ab19 TinyFPGA: update name of verilog "sketch". 2018-12-29 11:38:13 -08:00
Kyle Isom 0caf8118c0 TinyAdder: clean up top-level. 2018-12-29 11:10:02 -08:00
Kyle Isom 777c4529c2 TinyAdder: remove unused pins from constraints, add Makefile. 2018-12-29 11:08:26 -08:00
Kyle Isom b4d0799516 TinyAdder: Add docs, organise things, updated EAGLE files. 2018-12-29 10:49:04 -08:00
Kyle Isom 4770a2bd9c TinyFPGA/btled: a comment. 2018-12-29 10:11:22 -08:00
Kyle Isom 95827da3e1 TinyFPGA: add button-toggled LED. 2018-12-29 09:55:32 -08:00
Kyle Isom 1969718a5a Add CMSIS bluepill blink. 2018-12-29 07:05:25 -08:00
Kyle Isom f4645e0598 Add GEB pq checker. 2018-12-28 20:46:51 -08:00
Kyle Isom 2f086a2c28 Update FPGA experiments. 
+ Separate out into per-board directories.
+ Add icestick hello world.
+ Add TinyFPGA hello world, beacon, button-triggered LED, and TinyAdder.
+ Add platform constraint files for the iCEStick and TinyFPGA.
 2018-12-28 20:45:02 -08:00
Kyle Isom d47661659c TinyFPGA: add beacon 2018-12-28 15:44:47 -08:00
Kyle Isom 5e6838762e TinyAdder: add EAGLE files. 2018-12-28 14:53:06 -08:00
Kyle Isom 8080d93084 fpga: add TinyAdder rev1 2018-12-28 14:52:30 -08:00
Kyle Isom 729a5b3037 Start shipping problem. 2018-11-13 09:18:07 -08:00
Kyle Isom 22f71e1c99 ostep: add hw5 2018-09-05 18:33:20 -07:00
Kyle Isom 72f3484804 lr -> pr 2018-09-03 19:27:07 -07:00
Kyle Isom c1d6c41510 programming rust: finish chapter 2. 2018-09-03 19:27:07 -07:00
Kyle Isom 1f90323879 Start homework 5. 2018-08-29 21:04:35 -07:00
Kyle Isom 04b031c6f2 Start Rust OS stuff. 2018-08-21 14:55:28 -07:00
Kyle Isom 3e5c715493 qc: add README. 2018-06-11 09:43:41 -07:00
Kyle Isom c633b08cbd Add first QC experiments. 
Bell states in the Microsoft Quantum SDK and Rigetti's pyQuil.
 2018-06-11 09:41:09 -07:00
Kyle Isom 6ad979d28f Fix up bad git subtree import. 2018-06-11 09:39:27 -07:00
Kyle Isom e7c4c5ba49 misc/aqe: thinking about inference 2018-06-05 15:41:49 -07:00
Kyle Isom c87bbfdb93 Add Jupyter notebook with some examples. 2018-06-05 15:41:49 -07:00